Area and power-efficient hardware implementations are crucial for the widespread adoption of post-quantum cryptography (PQC) algorithms like FALCON. One of the main operations in FALCON is the Number Theoretic Transform (NTT), which needs to be performed with many prime numbers. Having one set of twiddle factors (TFs) for each prime makes storing all of these TFs impractical. In this paper, we propose an architecture for generating TFs on the fly for FALCON-oriented NTT, designed for area and power efficiency. Our approach dynamically generates TFs during NTT computations, significantly reducing on-chip memory requirements. The ASIC implementation results demonstrate significant improvements, with the proposed design reducing on-chip memory requirements by 99%, occupying 95% less area, and consuming 87.4% less power compared to the traditional ROM-based implementation. Furthermore, our design achieved a much higher maximum clock frequency, indicating superior performance in accessing twiddle factors. These findings highlight the potential of our proposed architecture for efficient hardware implementations of FALCON-based cryptographic systems.