3D Stacking of SiC Integrated Circuit Chips with Gold Wire Bonded Interconnects for Long-Duration High-Temperature Applications
Silicon carbide integrated circuits have been demonstrated to operate at high temperatures, such as ~460ºC at the Venus’ surface, for two months and for over a year at 500ºC. At these high temperatures, the SiC integrated circuits and sensors need to be packaged in quite different ways than those below 300ºC. In addition, to integrate more devices into the limited footprint of the high-temperature circuit board, 3D packaging is a notable advantage. In this work, 3D stacking of SiC chips using a gold wirebonding interconnect is investigated. The gold bonding wire is used due to its mechanical robustness and chemical inertness at high temperatures. Triple-stacked SiC chips are bonded to each other and to the gold contact pads on the alumina substrate with screen-printed gold pastes. The mechanical die shear test, wire pull tests, and interconnect electrical resistance tests are executed and analyzed before and after the 3D SiC chip packages are subject to a 600ºC thermal aging process in air for up to ten days. This 3D SiC chip packaging has promise for long-duration high temperatures (up to 600ºC) applications and may be potentially of use for applications such as Venus’s surface sensing and telemetry.
Email Address of Submitting Authorfengli@uidaho.edu
ORCID of Submitting Author0000-0001-9697-5002
Submitting Author's InstitutionUniversity of Idaho
Submitting Author's Country
- United States of America