A 0.33–2.61-GHz Rectifier With Expanded Dynamic Input Power Range Using Microstrip Impedance Compression Circuit

In this brief, an ultra-broadband rectifier with expanded dynamic input power range (IPR) for both wireless power transfer (WPT) and radio frequency energy-harvesting (RFEH) is proposed and analyzed. Expanded dynamic IPR and broadband impedance matching are realized by utilizing a microstrip transmission line impedance compression circuit (MTLICC) with the topology of the paralleled voltage doubler. A proof-of-concept prototype shows a dynamic IPR of 8.5–23.5 dBm, a frequency range of 0.33–2.61 GHz (fractional bandwidth of $155\%$ ), PCE is greater than 50%, and a peak PEC of 79.7% (achieved at an input-power level of 19 dBm). The measurement results are in good agreement with the simulation. Covering most 3G/4G/5G/ISM frequency bands, this design is promising for RF power transmission and energy harvesting in the age of the Internet of Things systems.

Therefore, it is critical to design rectifiers that can cover multiple frequency bands [2], [3]. A nonuniform transmission line is introduced to get a one-octave bandwidth [4]. In [5], a broadband rectifier employing a multi-stage LC matching-network is presented with a fractional bandwidth of 152.6% when an input power is 20 dBm. Its power-conversionefficiency (PCE) is over 50% from 0.39 GHz to 2.9 GHz. In [6], Dickson charge pumps are employed to increase bandwidth and improve DC voltage at the output loads simultaneously. On the other hand, the rectifiers applied to RFEH must also take into account the operation at different input powers [7].
There is a wide variation in power levels across frequency bands in different regions [8]. Therefore, designing rectifiers are important to provide capable of operating over an expanded dynamic IPR, which can get the solution in several recent works. For example, the IPR of rectifiers can be extended by using diodes with different properties in cooperation [9]. In [10], a second-order branched coupler was employed to effectively improve the dynamic IPR and bandwidth. However, the coupler introduces additional insertion loss and increases the rectifier size, limiting rectifier applications. Similarly, multiple rectifier units are employed to operate at different power levels [11], [12], [13], but the PCE is significantly reduced at the intersect points of different power ranges. Consequently, it is still a great challenge with practical importance to research on rectifiers with both multiple operating bands and a expanded dynamic IPR.
Herein, a method for designing ultra-broadband with expanded dynamic IPR rectifiers consisting of two voltage doubler and a microstrip transmission line impedance compression circuit (MTLICC) is presented, which achieves a high PCE over 50% for a expanded dynamic IPR of 8.5-23.5 dBm and a wide frequency range of 0.33-2.6 GHz, covering multiple cellular and ISM bands such as GSM 900 MHZ/1800 MHZ, 3G 2100 MHz and 2400 MHz WIFI bands.

A. Rectifier Topology
In a rectifier, the diodes operate as a non-linear device, with its input-impedance varying with input power, frequency 1549-7747 c 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information. and load resistor, where the input impedance variation can be mitigated by using a voltage doubler topology. The inputimpedance of a voltage-doubler rectifier is given by the following equation [14]: where θ on is the conduction angle, R s denotes the series resistance, while C j represents junction capacitance, V f is diode conduction voltage, and V D is DC-voltage across load resistor R load . From equation (2), the voltage doubler topology rectifier input impedance Z D is half of that of a single diode rectifier. Diode rectifiers suffer energy loss during rectification by three main mechanisms: • As a nonlinear device, diodes generate rich harmonics during rectification, and the harmonics disperse part of the energy. Some harmonics may be suppressed by careful circuit design. • The internal resistance of the diode introduces conduction loss. From equation (3), it can be seen that θ on is inversely proportional to R load . Therefore, it is generally desirable to have a higher R load . The smaller the conduction angle θ on is, the smaller the conduction loss is. • Because diode rectifiers have a variable input resistance in terms of frequency and input power, the circuit suffers from mismatch loss because the input is not always matched to the source impedance. The key to designing broadband and expanded dynamic IPR rectifiers is to reduce energy loss of rectifiers at different input power levels and frequencies. In this brief, we achieve this by a combination of a novel double-branch voltage doubler topology and a novel microstrip transmission line impedance compression circuit.
Figs. 1(a) and (b) illustrates the diagram of voltage doubler rectifier and double-branch voltage doubler rectifier array, respectively. Fig. 2 shows the input impedance Z D of the voltage doubler rectifier for different load resistor R load and different input frequencies at an input power of 16 dBm, where the real-part of input impedance Z D is relatively constant over  a broad frequency of 0-3 GHz for various R load . The imaginary part of Z D gradually changes from inductive to capacitive as R load increases. Fig. 3 shows the load resistors R load versus PCE for the voltage doubler rectifier at different input power levels. In particular, for R load = 200 , the real part of Z in is approximately 50 while the imaginary part is inductive. In this case, good matching can be achieved by simply connecting a capacitance in series. However, due to the small R load , the conduction loss of the rectifier is higher and the PCE is significantly lower at lower input-power levels.
To mitigate this, a two-branch voltage doubler topology ( Fig. 1(b)) is proposed, whose input-impedance Z in of the rectifier is half of the single voltage doubler rectifier. As such, a higher R load can be chosen to match the real-part of the input-impedance over a larger range of frequency and input power.
This topology structure enables greater load resistors to be chosen, where parallel connection not only alleviates the fluctuations of input impedance caused by frequency and input power variation, but also extends the IPR of the rectifier.

B. Microstrip Transmission Line Impedance Compression Circuit Design
After the paralleled voltage doubler topology, the input impedance of the rectifier array is relatively smooth already but still exhibits capacitance, which will result in deterioration of rectifier performance in the target frequency band and input power levels. In this situation, traditional L-or T-shaped matching networks, which can only operate in narrow bands, would not only increase the complexity of the rectifier structure but might even reduce the relevant performance of the rectifier. Hence, to further reduce the input impedance variation range, we propose a MTLICC that evolves from the resistor compress network [15] to construct our devised rectifier in Fig. 4, which has two sub-rectifier cells and a MTLICC. Each sub-rectifier cell consists of a DC blocking capacitor, a DC-pass filter capacitor, a load resistor, and an HSMS286C Schottky diode. The MTLICC consists of five microstrip transmission lines to create a two-branch configurated rectifier. By adjusting the electrical length of the input impedance at the rear-end of the upper and lower branches to 90 • + θ and 90 • − θ , respectively, the imaginary part of the rectifier input impedance can be eliminated when the two branches are connected in parallel, thus reducing the energy loss caused by the impedance mismatch.
Detailed analysis of the impedance compression characteristics of the MTLICC in the rectifier is given below. The circuit structure of the rectifier with (Rec2) and without (Rec1) the MTLICC can be simplified and are shown in Fig. 5 by ignoring the transmission line TL4 and taking the effects of TL1 and TL3 into the rectifier rear-end. Then, It is assumed that R load1 equals R load2 . The input impedance of the upper and lower branches of the rectifier can be equated to Z L1 and Z L2 , respectively, and Next, the microstrip transmission line TL2, which is wider at both ends of the TL1 and TL5, is relatively narrower on its own and can be approximated as an inductor jX m , which reduces the variation of the imaginary part of Z in . TL1 and TL3 are used to regulate the rear-end impedance. Till now, TL2 transforms the input-impedance of the upper-branch to where Z 2 and θ 2 are respectively characteristic impedance and electrical length of TL2. From simulation, we have TL5 is used to transform Z in to 50 .
where Z 5 and θ 5 are respectively characteristic impedance and electrical length of TL5. Here, we have Z 5 = 61 and θ 5 = 13.8 • at 2.4 GHz. Note that it's difficult to completely eliminate the imaginary part of the input-impedance over a wide frequency and expanded dynamic IPR. The MTLICC's function is to compress the impedance as close to 50 as possible.
The specific variations of the simulated values of the input impedance of the proposed rectifier array are recorded in Table I. Fig. 6 illustrates the input impedance variation of the devised rectifier with and without the MTLICC. Note that the MTLICC balances the matching characteristics of the devised rectifier at low power levels and high power levels. Fig. 7 gives the PCE for the two rectifiers at three different inputpower levels, showing the compression characteristics of the MTLICC. In summary, for the same bandwidth, the expanded dynamic IPR of the devised rectifier is extended by 4.5 dB compared to the rectifier without MTLICC.

III. IMPLEMENTATION AND MEASUREMENTS
In order to further verify the devised ultra-broadband rectifier array with a expanded dynamic IPR using MTLICC, it was simulated and optimized in Keysight Advanced Design System (ADS). Packaging parameters are considered in the design process. The rectifier is designed and fabricated on a F4B (tanD = 0.002, r = 2.55) substrate with a thickness of 0.764 mm. The entire rectifier circuit is 8 × 15 mm 2 . Detailed parameters are presented in Fig. 8 with a phototype of the fabricated rectifier. Two HSMS286C Schottky diodes are used, and the capacitors are 15 pF and 100 pF (Murata's GRM18 series). The load resistance of the up and down branches are 600 and 460 , respectively. It is also worth noting that the above parameters are only one value for the rectifier. The load resistors can also take other values, or an external DC-DC converter circuit at the output of the rectifier can convert output voltage to other levels to suit for different application scenarios.
RF signal generators are used to provide the input RF signal and the voltages on the two DC load resistors are measured with a multi-channel digital multimeter. The simulated and measured results are in basic agreement, and the discrepancies may be caused by parasitic effects of the capacitors and inaccurate modeling of the diodes. Fig. 9 shows the measured results. The RF-energy to DC-energy PCE is gotten from the following equation   In Fig. 9, we presente the PCE of the devised at input power levels of 8.5 dBm, 14 dBm, 20 dBm and 23.5 dBm, respectively. Fig. 10 shows the simulated PCE at an input-power of 23.5 dBm and input-frequency of 2.4 GHz. With the addition of the MTLICC, the input-impedance changes of the devised two sub-rectifiers, and the rectifier's PCE changes accordingly. Fig. 11 presents PCEs of the proposed rectifier versus different input powers and frequencies. While the input-power levels varies between 8.5 dBm and 23.5 dBm, the PCE is greater than  It is worth noting that larger bandwidths can be obtained at some specific powers. In general, the simulation and measurement results are in good agreement. Discrepancies may be caused by parasitics of the capacitors and inaccurate modeling of the diodes.
In order to demonstrate the effectiveness of the proposed strategy. The performance of the rectifier is compared to several earlier relevant works in Table II and show clear advantages in terms of bandwidth and input power range.

IV. CONCLUSION
A strategy for developing a super-broadband microwave rectifier using MTLICC with a expanded dynamic input power range is proposed. On the basis of the proposed strategy, the rectifier array prototype is fabricated and measured. The proposed rectifier achieved a PCE > 50% over the input power ranges of 8.5-23.5 dBm at 0.33-2.6 GHz, while the maximum PCE was 79.7%. In addition, the devised rectifier has the advantages of compact dimensions, broad bandwidth, wide input power range and high efficiency. These results are of great interest to application for WPT and RFEH systems.