2020_TMTT_DSRC_PA_Rev5.pdf (1.63 MB)

A 5.8 GHz 10 dBm Linear CMOS Power Amplifier with Reconfigurable Load Pull Network for DSRC

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posted on 2022-07-01, 13:33 authored by Yasser QaragoezYasser Qaragoez

In this paper, a novel reconfigurable 5.8 GHz linear power amplifier with a digital pulse-shaping filter (PSF) to improve the spurious is presented for dedicated short-range communication (DSRC) transceivers. An on-chip reconfigurable load transfer network (LTN) is able to match the output load variations to PA while keeping output return loss blow -10 dB. Furthermore, LTN improves the stability by varying quality factor of LTN for different operation conditions. The power amplifier consists of a Class-AB driver stage and a cascode topology for the PA core. To improve the spurious of the PA and controlling modulation index a gaussian-based digital pulseshaping filter is implemented which has achieved an occupied bandwidth (OCB) of less than 2 MHz. Realized in a 0.13-m CMOS technology with an area of 1.1 mm2, the power amplifier achieves 10 dBm and 25 dB output power and dynamic range, respectively. PA dissipates 76 mA from 3-V supply voltage.


Email Address of Submitting Author

Submitting Author's Institution

Sungkyunkwan University

Submitting Author's Country

  • Korea, Republic of (South Korea)