A Comprehensive Review of Design Challenges and Techniques for Nanoscale SRAM: A Cell Perspective

In order to meet the ultra-low power requirement of modern digital systems, voltage scaling
is a fruitful technique that is widely adopted. However, the voltage scaling at ultra-scaled technologies
significantly affect the stability of an Static Random Access Memory (SRAM) cell. This work provides
an extensive review of various designs and techniques for solving issues related to SRAM cell stability.
Decoupling the read operation is a commonly used technique for addressing read stability issue. Modified
Schmitt-trigger based cell core, loop-cutting and additional discharge path based techniques have also been
employed in the literature to enhance the read stability. However, the write-ability and stability of halfselected (HS) cells have been compromised in some of these technique. For write-ability enhancement,
most of the techniques involve either weakening of pull-up/pull-down devices (to reduce the current
responsible for storing the data) or strengthening of access transistors (to enhance the write current). It
includes VDD/VSS -cut off or -floating, feedback cutting, multi-Vth write assist based cells. Apart from
discussing the alternative bitcells, we also cover several peripheral read/write assist techniques. WL underdrive (WLUD) and dynamic WLUD are effective read assist techniques. WL -boost, WL -delayed boost,
VDD-floating/lowering, transient VDD collapse, VSS raised, dual split control-VSS raised and negative BL
(NBL) are among the peripheral techniques for enhancing write-ability. Furthermore, various techniques
for mitigating the HS cell issues, such as write-back, column decoupled local wordline, modified bitinterleaving array architecture are discussed. Finally, the Cross-point selection based cell accessing in-built
technique is illustrated. Through summary tables, conclusions are also derived for suggesting a circuit of
choice for various categories.