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A Computationally Efficient Compact Model for Ferroelectric FinFETs Switching with Asymmetric Non-Periodic Input Signals

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posted on 22.02.2022, 03:22 by Amol GaidhaneAmol Gaidhane, Raghvendra Dangi, Shubham SahayShubham Sahay, Amit Verma, Yogesh Singh Chauhan
In this paper, we develop a Verilog-A implementable compact model for the dynamic switching of ferroelectric Fin-FETs (Fe-FinFETs) for asymmetric non-periodic input signals. We use the multi-domain Preisach Model to capture the saturated P-E loop of the ferroelectric capacitors. In addition to the saturation loop, we model the history dependent minor loop paths in the P-E by tracing input signals’ turning points. To capture the input signals’ turning points, we propose an R-C circuit based approach in this work. We calibrate our proposed model with the experimental data, and it accurately captures the history effect and minor loop paths of the ferroelectric capacitor. Furthermore, the elimination of storage of each turning point makes the proposed model computationally efficient compared with the previous implementations. We also demonstrate the unique electrical characteristics of Fe-FinFETs by integrating the developed compact model of Fe-Cap with the BSIM-CMG model of 7nm FinFET.

Funding

Swarnajayanti Fellowship (Grant No. – DST/SJF/ETA-02/2017-18) and FIST Scheme (Grant No. – SR/FST/ETII-072/2016) of the Department of Science, India.

History

Email Address of Submitting Author

ssahay@iitk.ac.in

ORCID of Submitting Author

0000-0001-9992-3240

Submitting Author's Institution

Indian Institute of Technology Kanpur

Submitting Author's Country

India

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