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A Connected Component Labelling algorithm for multi-pixel per clock cycle video stream

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posted on 2021-05-24, 20:23 authored by Marcin Kowalczyk, Tomasz KryjakTomasz Kryjak
This work describes the hardware implementation of a connected component labelling (CCL) module in reprogammable logic. The main novelty of the design is the ``full'', i.e. without any simplifications, support of a 4 pixel per clock format (4 ppc) and real-time processing of a 4K/UltraHD video stream (3840 x 2160 pixels) at 60 frames per second. To achieve this, a special labelling method was designed and a functionality that stops the input data stream in order to process pixel groups which require writing more than one merger into the equivalence table. The proposed module was verified in simulation and in hardware on the Xilinx Zynq Ultrascale+ MPSoC chip on the ZCU104 evaluation board.


National Science Centre project no. 2016/23/D/ST6/01389


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ORCID of Submitting Author


Submitting Author's Institution

AGH University of Science and Technology

Submitting Author's Country

  • Poland

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