A Differential Delay Cell for Ring Oscillators

This paper presents a differential delay cell (DDC) for a 3-stage current-starved ring voltage-controlled oscillator (CSRVCO). In the proposed delay cell, pass transistors and a pair of back-to-back transistors are connected in a symmetric structure that helps get less jittery output by providing similar charging and discharging paths from the load capacitor. The current flows from similar paths with the same type and number of transistors in the proposed DDC-based CSRVCO. For verifying the DDC operation, the 3-stage CSRVCO using the proposed DDC is implemented with a standard 65nm CMOS technology with 1V supply. Post-layout simulation results confirm the correct operation of the proposed DDC using the CSRVCO with minimal jitter at the output. The proposed CSRVCO can be tuned from 0.88 GHz to 2.76 GHz. The phase noise of -94.54 dBc Hz was measured at 1MHz offset frequency for the center frequency of 2.76 GHz. The CSRVCO was designed using the proposed DDC occupied area 1198.43 μm2, and dissipated power is 5.19mW.