A Floating Memristor Emulator with Inverse Frequency Characteristic

This paper presents a novel memristor emulator with inverse frequency characteristics. This emulator is configured using only four NMOS transistors and an external capacitor. The proposed memristor emulator acts as a memristor and generates a pinched hysteresis loop (PHL). Its lobe area increases with an increase in the operating frequency. Its numerical analysis is performed using Cadence Virtuoso employing TSMC 180nm PDKs. The inverse frequency behaviour of the proposed memristor emulator is evaluated at different operating frequencies, temperatures, and other process corners. The correctness and reliability of the proposed emulator are validated through post-layout simulation. The area utilization and power consumption of the proposed emulator are 354.66 µm² and 291.78 µW . Its functionality is verified by conducting a physical experiment using ALD1106 n-channel MOSFETs. Its applicability is further validated by designing a chaotic oscillator and a NOR gate.