A High-Level Approach for Energy Efficiency Improvement of FPGAs by Voltage Trimming

This paper proposes a solution that makes voltage scaling possible by simply using HLS tools provided by vendor to improve energy efficiency of FPGAs by 2x. Chip manufacturers define voltage margins on top of the “best-case” operational voltage of their chips to ensure reliable worst case functionality. The margins guarantee correct-ness of operation, but at the cost of performance and power efficiency. Violating the margins is tempting to save energy, but might lead to timing errors. This paper proposes an algorithmic solution that enables reliable removal of the margins by detecting errors on-the-fly. In contrast to previous approaches that require special hardware to detect timing errors, the proposed method is fully implementable using High Level Synthesis tools without reliance on additional hardware. The approach is demonstrated using a32×32matrix-matrix multiplication and a simple multi-layer neural network implemented on two Xilinx ZC702Field-Programmable-Gate-Array (FPGA) System-on-Chip (SoC)platforms, showcasing its utility in detecting errors that may originate from different sources of logic circuity, clock tree and memory. Results show that the energy dissipation is halved, while the implementation is clocked at 2.5x faster than specified by the design tool of the vendor.