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A Laplace Domain Model Implementation in System Verilog for Top Level Functional Verification

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posted on 2023-06-16, 15:14 authored by Daniel McMitchellDaniel McMitchell

In top level functional verification of mixed-signal VLSI systems, special efforts are required to adequately model the design’s analogue portions to maximise verification coverage in a reasonable regression runtime. Although generally one will want to avoid modelling analogue frequency domain behaviour where possible, in some contexts – including, for stability reasons, closed-loop mixed-signal systems – it may be necessary. This paper presents a System Verilog implementation of a system described by arbitrary Laplace coefficient parameters; appropriate for modelling a frequency-dependent analogue path.


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  • United Kingdom