A Laplace Domain Model Implementation in System Verilog for Top Level Functional Verification
In top level functional verification of mixed-signal VLSI systems, special efforts are required to adequately model the design’s analogue portions to maximise verification coverage in a reasonable regression runtime. Although generally one will want to avoid modelling analogue frequency domain behaviour where possible, in some contexts – including, for stability reasons, closed-loop mixed-signal systems – it may be necessary. This paper presents a System Verilog implementation of a system described by arbitrary Laplace coefficient parameters; appropriate for modelling a frequency-dependent analogue path.
Email Address of Submitting Authordmcmitchell@gmail.com
ORCID of Submitting Author0009-0005-4336-0027
Submitting Author's InstitutionDukosi
Submitting Author's Country
- United Kingdom