A New Approach to Improve the Voltage Conversion Ratio in Topological Switched-Capacitor DC–DC Converters Using Negator Stage

This brief provides a simple yet novel structure to achieve voltage conversion ratio (VCR) that exceeds the theoretical attainable VCR of topological switched-capacitor DC-DC converters (SCC). Typically, the SCC terminals are connected to the input voltage, the output voltage, or the ground reference. The proposed structure in this brief utilizes the ground-connected terminals and instead connecting them to negative input voltage provided by a negator stage. Here, two types of SCC are used as case studies: Series-parallel (SPSC) and Fibonacci (FSC). The model for the proposed structure is constructed and verified experimentally using 3-stage SPSC and FSC. The experimental results are in good agreement with the proposed model with an error of less than 5% in all cases. The VCR obtained from the proposed structure exceeds the theoretical limits of conventional topological structures.


I. INTRODUCTION
T HE SWITCHED-CAPACITOR DC-DC converter (SCC) has been very attractive due to its magnetic-less feature which lends themselves to IC integration and high power density [1], [2]. As shown in Fig. 1, the SCC comprises a switch network that can be implemented using transistors or diodes, flying capacitors to pump charges from one stage to another, and a control circuit that drives the switch network. In general, the SCC can be used to buck/boost the input voltage [1], [3]. Considering the way it is synthesized, SCC can be categorized into two main groups: topological and non-topological converters. The topological SCC is synthesized in a systematic way based on well-established structures such as the Dickson charge pump, series-parallel (SPSC), Fibonacci (FSC), exponential charge pump and binary SCC [4], [5], [6], [7]. On the other hand, the switch network and the flying capacitors in Manuscript  the non-topological SCC are structured on an ad hoc way [8]. This brief discusses only the topological SCC structures. The theory of SCC has been extensively investigated [9], [10], [11]. As a milestone, the fundamental limit of the SCC is proposed in [10] and is further generalized in [11]. The fundamental limit relates the maximum attainable voltage conversion ratio (VCR), VCR = v out /v in , for certain number of flying capacitors and switches. The fundamental limit shows that the FSC achieves the highest VCR with the minimum number of components count [10]. The fundamental limit is useful in synthesizing SCC to achieve certain conversions [12], [13]. Nevertheless, for applications that require high VCR [14], resonant converters that utilize both inductors and capacitors are commonly used. Alternatively, SCC can be used by increasing the number of converter stages. However, cascading SCC stages require more components that contribute to additional power losses [15].
Recently, [16] proposed to utilize a self-generated negative voltage (V NEG ) to improve the transient response of buck converters. While the concept of using negative voltage improves the buck converter performance, generating the negative voltage is achieved using inverting buck-boost converter which requires an inductor and dedicated controller circuit to control the duty cycle and drive the switches. For example, the loading switches (SE3 and SE4) need to be turned on when −1 < V NEG < −5V. In addition, the generated V NEG improves the input voltage of the buck by only 0.6x as indicated in [16], i.e., V NEG = −1.5V.
1549-7747 c 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information. This brief proposes a new, yet simple technique to increase the VCR of a topological SCC beyond the theoretical gain limits with fewer components count by utilizing the concept of inserting negative voltage. In contrast to [16], the negative voltage is generated using a negator stage using one flying capacitor and four switches. The switches are driven by the same converter's controller, hence no additional circuit requirements. The negator stage is inserted prior to the SCC and feeds a negative voltage to some of the SCC terminals as illustrated in Fig. 2.
This brief is structured as follows: Section II discusses the design of the proposed structure of SCC with high VCR focusing on two topologies: SPSC and FSC. The experimental results of the proposed designs are presented in Section III. Finally, conclusions are drawn in Section IV.

II. PROPOSED DESIGN
The equivalent circuit model of the SCC is shown in Fig. 1. The ideal transformer models the ideal VCR (n = VCR) of the converter and R eq quantifies the SCC losses including conduction and switching losses [15]. Using this model, the output voltage can easily be written as: V out = nV in − I out R eq . Note that, n is considered the main steady-state parameter that determines the VCR of the converter. Hence, lossless SCC is assumed in this brief, i.e., R eq = 0, to thoroughly study the effect of the proposed structure on the ideal VCR.

A. Steady-State Analysis Assuming Lossless SCC
In general, conventional SCC topologies can be designed to achieve high VCR. Nevertheless, the conventional way of synthesizing SCC requires more components count. For example, an ideal VCR of five, i.e., v out = 5v in , can be achieved using four stages of SPSC, and/or three stages of FSC, as follows [10]: where k is the number of flying capacitors and F k is k th the Fibonacci number. Note that, (1) and (2) neglect the converter losses and consider only the ideal VCR.
In [12], a way to conceptualize and synthesize SCC using terminal weight is presented. Basically, for a topological SCC like SPSC or FSC with j number of terminals, the j th terminal weight (w j ) can be assigned according to the attainable VCR. Note that, the terminal weight (w j ) can be only a positive or negative integer number and it is assigned mathematically to satisfy the following condition: where k is the number of flying capacitors used in the converter, and k + 2 represents the number of all terminals. Usually, the first terminal of the SCC is assigned a weight that is equal to the maximum attainable VCR, i.e., w 1 = VCR max . For example, 4-stage SPSC has a maximum VCR of five and hence w 1 = 5. Furthermore, the weight of the last terminal is always −1, which implies that w k+2 = −1. The other terminals are assigned weights based on the SCC topology [12], [13]. Therefore, (3) can be modified to be: Considering the multiple-input, multiple-output (MIMO) SCC, the concept of terminal weight can be used to relate the terminal voltages in the converter as follows [11], [17]: where p is the number of inputs, q is the number of outputs, v g is the input voltage, v o is the output voltage and w is the terminal weight. This brief studies the single-input single-output (SISO) SCC boost operation. Therefore, the input voltage is connected to the first terminal and the output voltage is connected to the last terminal. By combining (4) and (5), the output voltage can be written as: where w 1 = VCR max , w j < 0 and v j is the voltage at the j th terminal that is usually set to zero, i.e., the terminal is grounded, in the conventional SCC topologies. The proposed structure, depicted in Fig. 2, uses a negator to provide a negative input voltage to one or more of the SCC terminals to achieve a higher VCR. If the negative input voltage is connected to all remaining SCC terminals, i.e., v j = −v in , (6) suggests that the output voltage will increase and can be calculated as: Note that, the model in (7) assumes that the output voltage of the negator stage equals −v in . Nevertheless, this voltage can be slightly less due to the conduction and switching losses of the negator stage. Therefore, without loss of generality, the output voltage of the negator, v negator , can be used to compute the output voltage of the converter as: In this brief, SPSC and FSC are chosen, which represent the linear and non-linear SCCs, respectively. Using (7), the output voltage of SPSC and FSC can be written as: As shown in Fig. 3, the proposed SPSC and FSC outperform the conventional counterparts by achieving higher VCR. For low number of stages, the VCR of the conventional and proposed structures are very close to each other. However, the VCR is growing drastically as the number of stages increases for the FSC case. On the other hand, the VCR increases linearly for the SPSC but with a steeper slope compared to the conventional one. In general, the proposed structures increase the VCR of almost (k − 2) for SPSC and k+1 j=2 |F j | for FSC compared to the conventional design counterparts. Note that, one can consider the negator as an additional stage, nevertheless, the proposed high VCR structure still outperforms the conventional SCC. For example, a 4-stage SPSC achieves VCR = 5, while it can be increased to VCR = 7 using the proposed structure with the 3-stage SPSC and the negator stage.
The proposed high VCR configuration is verified using 3stage SPSC and 3-stage FSC depicted in Fig. 4. The switches are driven using two complementary non-overlapping clocks, S a and S b . To better explain the operation of the proposed converters, consider steady-state for the charge in the flying capacitors in two main phases, charging and pumping, throughout a complete switching cycle.
During the charging phase, which occurs when S a is high and S b is low, all flying capacitors are fully charged. In the pumping phase, S a is High and S b is low, the charges are pumped to the output terminal. Moreover, the negator is assumed to be in steady-state, which implies that the voltage at nodes x and y equals −V in . The equivalent circuits for both phases are shown in Fig. 4(c) & (d) for SPSC and Fig. 4

(e) & (f) for FSC.
Due to the capacitor charge balance, the voltage across capacitors remains effectively the same for one complete switching cycle. Therefore, for SPSC charging phase shown in Fig. 4(c), V C1 = V C2 = V C3 = 2V in , and during the pumping phase, Fig. 4(d), the output voltage can be found to be 7V in . Similarly for the FSC case, Fig. 4(e) shows that V C1 = 2V in and V C2 = V C3 − 2V in . On the other hand, V C2 = 4V in during the pumping phase, Fig. 4(f), which implies that V C3 = 6V in . Hence, the output voltage of the FSC is calculated as 9V in . Finally, it is worth mentioning that the stress voltage of the capacitors and switches in the proposed designs is increased due to the availability of the −V in . For example, the stress voltage for the SPSC flying capacitors, C 1 , C 2 and C 3 , is now 2V in compared to only V in in the conventional SPSC. For high voltage applications, this increase in the stress voltage needs to be studied carefully to avoid additional overhead costs.

B. Efficiency Analysis Assuming Lossy SCC
In the previous subsection, the analysis is carried out assuming lossless SCC, viz R eq = 0. Here, the efficiency analysis is compare the conventional SCC design to the proposed one. In general, the converter efficiency can be quantified as: where P out = I 2 out R L and P loss is power losses due to the conduction and switching. The losses can be written as: P loss = I 2 out R eq .Therefore, (11) can be simplified to: The switching limits and vector analysis can be used to quantify R eq [15]. On the other hand, thorough details of SCC design and analysis using off-the-shelf components can be found in [18]. However, such analysis is beyond the scope of this brief. Instead, the steady-state model shown in Fig. 1 can be utilized to find R eq , which implies: Therefore, by using R L = V out /i out and substituting (13) in (12), the converter efficiency can be simplified to: The conventional and proposed converters are simulated using SPICE simulator with f s = 100 kHz, analog switches with R on = 10 , 0.1μF for all flying and output capacitors. The converter efficiency is calculated based on (14). Fig. 5 shows the efficiency for different loads. It can be seen that the proposed converter outperforms the 4-stage converter for both cases, SPSC and FSC.
The effective series resistance (ESR) of the capacitors has also some effects on the converter efficiency, especially for high-power applications. Using SPICE simulator, Table I    the ESR of the 0.1μF capacitors is swept between 0 , i.e., ideal case, to 100 with fixed load resistance of 100k . Other parameters are kept the same, e.g., f s = 100 kHz and analog switches with R on = 10 . It can be seen that the ESR minimizes the converter efficiency slightly for low ESR. For extreme cases, the converter efficiency of the conventional SPSC is degraded by 1.73% due to the ESR, viz. from 99.47% in the ideal scenario to 97.74% for ESR of 100 , while it is about 1.31% for the proposed structure. On the other hand, the difference in the converter efficiency for the 4-stage and proposed FSC is about 5.53% and 2.4%, respectively. Therefore, the effect of ESR is minimal in the proposed structure compared to the conventional designs. In general, the ESR can be optimized for high converter efficiency.

III. RESULTS AND DISCUSSION
To test the model proposed in (7), 3-stage SPSC and 3-stage FSC are built as shown in Fig. 4 and tested using the experimental setup shown in Fig. 6. The converters are implemented using MC14066B analog switches, 10 μ F capacitors as flying and output capacitors, and 1 M load. The switches are driven by two non-overlapping complementary clocks, S a and S b , generated from the microcontroller and switching at 10 kHz with 124 ns deadtime which is verified using the TDS2021C oscilloscope [17]. The EL302T power supply is used to provide the input voltage to the converters. The voltage measured at the output of the negator stage is approximately 35 − 50mV lower than the input voltage. The quiescent current of converter is measured around 8.5 μA. Fig. 6 shows one of the experiments for FSC: input voltage, negator output voltage, and FSC output voltage are measured using digital multimeters (DMM) and are found to be 0.3V, −0.26V, and 2.57V, respectively. Using (8), the voltage is expected to be 2.54V which results in 1.17% error. With the same procedure, the experiment is conducted by varying the input voltage between 0.1 − 0.5V and measuring the output voltage for the proposed  SPSC and FSC. Moreover, using the output voltage expected by the model in (8), the error is calculated as follows: The results are illustrated in Fig. 7 showing the output voltage versus the input voltage. It can be seen that the experimental results agree well with the models with an error of less than 5% for all cases.

IV. CONCLUSION
In this brief, a new configuration was proposed to achieve a high VCR for topological SCC by adding a negator stage to the converter. A model that predicts the ideal VCR for the proposed structure was presented and verified experimentally using two different topologies: SPSC and FSC. The VCR increased for both cases by adopting the proposed configuration. The proposed structure is studied using topological SCC, however, it can be further investigated in non-topological SCC. which may lead to highly efficient converters.