A Novel Low-Power Encryption Scheme Based on Chaotic Dynamic Triple Pendulum System for Wide Range of Applications

— Recent advancements in the domain of quantum computing are posing a security threat to the classical cryptography algorithms. Popular symmetric and asymmetric cryptosystems including RSA, ECC, DES, Difﬁe-Hellman etc. can be broken by a quantum computer executing Shors and Grovers algorithms. This motivated scientiﬁc community to design newer encryption schemes to address security vulnerabilities. Hash, Code, Lattice, Multivariate Polynomial based cryptography algorithms, known as post-quantum cryptography algorithms (PQC), exhibit resistance against classical as well as quantum crypto-attacks. Apart from these PQC algorithms, a relatively new method of constructing cryptosystems utilizing the unpredictability property of discrete chaotic dynamic systems has become noteworthy from the practical perspective. In this paper, we present a novel approach to design an encryption scheme based on the chaotic dynamic physical system, which is derived from a mechanical model depicting nonlinear dynamics and exhibits resistance against various attacks. The effectiveness of the proposed cryptography scheme is validated against various standard tests, such as Lyapunov exponents test, bifurcation diagrams, sensitivity to parametric and to initial values, ergodicity, collision test, NIST, diehard randomness test etc. This algorithm is also veriﬁed through an FPGA implementation to assess its usage in low power high throughput applications as well. The power consumption and resource utilization of the proposed design are 56 % and 72 . 6 %, respectively, as compared to other known methods while operating at 628 . 14 MHz. It is observed that the proposed design can work efﬁciently with various wide range of applications. It is observed that the proposed design can work efﬁciently with various wide range of applications. The average power and area of its ASIC implementation at 180 nm technology are 61 . 8836 mW and 0 . 20374 mm 2 at 250 MHz, respectively.


INTRODUCTION
T HE enhancement of computing power and the rise of quantum computing have made many widely adopted conventional encryption schemes vulnerable. Due to this scientific community is compel to find a suitable solution to address this issue. Chaotic dynamic system based algorithms categorized as PQC algorithms can act as viable solution to this threat. There is no known successful quantum computer based attacks against chaos based encryption schemes [1]. The main advantages of deterministic chaotic systems are higher degree of unpredictability, ergodicity, high sensitivity to initial conditions and control parameters, close resemblance with true randomness and unstable long aperiodic orbits. These chaotic properties can be employed in synchronization and control, communication, cryptography, neural network, etc. [2], [3], [4]. These systems are distinguished by their high sensitivity to initial conditions, statistical similarity to random signals and a continuous Manuscript received June -, 2021; revised --, --. broadband power spectrum. All this has garnered interest from cryptanalysts to propose various chaos based cryptographic systems [5], [6]. The chaos based cryptosystems can be subdivided into two classes. In the first class, a chaotic system is numerically iterated over a period by employing a message as an initial data [7], whereas, in the second class, a message is scrambled with a chaotic dynamic function. The relevance and usefulness of chaos have been demonstrated through comparative studies employing characteristics of a chaotic system and the requirement of a strong cipher [6], [7]. Cryptographically similar domains of chaotic systems can be utilized to generate a strong cipher for a strong cryptosystem.
Designing cryptographic schemes based on chaotic dynamics can be divided into two steps. In the first step, an encryption algorithm is modeled based on analog chaotic dynamic systems. Thereafter, discretization with finiteprecision is introduced during hardware implementation. It is to mention that discretization is the main trade-off between security and resource utilization. As we know, the method of synchronization of multiple chaotic systems is applied in some of the earliest cryptography applications. Among the chaotic maps, the piece-wise linear chaotic map (PLCM) [8], [9], [10] is the simplest one-dimensional system and can be implemented easily, but it is prone to security vulnerabilities due to smaller keyspace. Various modifications and variants of 1-D PLCM, such as piece-wise nonlinear chaotic maps, algorithms based on logistic maps [11], [12], polynomial chaotic maps are reported in literature. Now-a-days, many real world chaotic phenomenon are being modeled to get ideal chaotic characteristics; therefore, physical chaotic dynamical systems have become an imperative area of research in chaos based cryptography [13] [14].
For strengthening the security and to increase the speed of chaotic cryptosystems, a combination of multiple one dimensional algorithms are used. For example, in [15], a combination of polynomial chaotic map and the piecewise nonlinear chaotic map is employed to enhance the speed and security of a cryptosystem. It is to mention that various chaotic block cipher encryption schemes are also developed. A chaotic tent map based single iterative encryption scheme is proposed in [16], which is further generalized in [17], and multiple iterative based dynamical chaotic system models are presented in [18]. A novel symmetric block cipher algorithm based on invertible two dimensional chaotic maps on a torus is presented in [19], whereas, schemes formulated by employing iterative logistic equation and synchronized chaotic systems are discussed in [20] and [21], respectively. In another approach, different chaotic attractors for a random chunk of binary plain-text data is presented [22] in order to implement chaotic based encryption scheme.
As per our knowledge, only a few chaotic map-based image and video encryption schemes have been developed in the past. Some of these methods are mentioned as follows. In [13], a new hyperchaotic temperature fluctuation model based on the circuit analysis is proposed for an image encryption. Simple first order differential equations (ẋ = z;ẏ = −z(ay + by 2 + xz);ż = x 2 + y 2 − |x| − 1) based a new 3D chaotic system employing a peanut-shaped symmetric equilibrium curve is reported in [23]. A nonlinear continuous-time dynamical chaotic system based on two circles of equilibrium points and its multistability is discussed in [24]. As mentioned above, all these chaotic systems are utilized for image and video encryption only and there is no general-purpose chaotic dynamic system based cryptosystem exist. With the advent of smart systems incorporating Internet-of-Things (IoT) devices, data (or information) security has become of utmost importance. Internet of Everything (IoE) is the future and it demands a system to have very high security, energy efficiency and reliability. Therefore, it has become imperative to design a general purpose low power cryptosystem, which can be used in various applications ranging from IoT based smart systems to high throughput low latency systems. In this paper, we proposed a novel and generic chaos-based low power cryptosystem to address above mentioned issues, which is based on a chaotic triple pendulum system. This novel algorithm is also implemented on FPGA as well as on ASIC and is compared with other state of the art methods reported in the literature. Details of our proposed algorithm is presented in the subsequent sections.
The organization of the manuscript is as follows. Section II illustrates a step-wise approach and methodology to design a triple pendulum based cryptography algorithm. In Section III, formulations of chaotic double and triple pendulum dynamic systems are presented with case studies. Section IV presents Lyapunov exponents test and bifurcation diagrams to test chaotic behavior of the proposed triple pendulum based chaotic dynamic system. Later, encryption and decryption algorithms are also depicted in the same section. The details of hardware implementation are exhibited in section V. Thereafter, detailed discussion on the results obtained on FPGA and ASIC to validate effectiveness of the proposed method, and various tests, such as sensitivity to parametric and to initial values, ergodicity, collision test, NIST, diehard randomness test conducted to assure chaotic nature of the proposed method are described in section VI. Finally, a conclusion is drawn in Section VII.

PROPOSED APPROACH
The proposed research focuses on implementing a new chaos-based encryption-decryption technique on Field Programmable Gate Array (FPGA) and as an Application Specific Integrated Circuit (ASIC). Unlike traditional cryptographic methods, we aim to design a system in such a way that it should not only be less resource-intense and computationally efficient but also provide a reasonable degree of security. For achieving this goal, necessary steps to be performed along with design and implementation are given below.   The motivation behind employing the proposed algorithms for encryption and decryption is based on Baptistatype encryption-decryption scheme. It is described using an interval-partitioning of chaotic orbits of a 1D logistic map, which enables construction of very fast and secure encryption-decryption schemes, because of its less complex structure. The main objective of our scheme is to first map text characters to numerical values and, then algorithms are applied to encrypt the message. Decryption is performed by iterating a chaotic map and, then corresponding symbols for numerical values are obtained by inverting the process. After referring literature, we have decided to employ a compound triple-pendulum model for creating desired chaotic map in our cryptosystem. Since, input to the system is a plain message, the system parameter(s) and additionally the initial conditions of a dynamical system are assumed to be the part of the secret key. After analyzing a triple-pendulum system, a valid set of keys for encryption and decryption is generated. The entire mechanical model is implemented on an FPGA along with a custom ALU and a control unit adhering to the specifications of our proposed system. After successful validation of the design on an FPGA, it is realized using Semi Conductor Laboratory (SCL) 180nm Bulk CMOS technology.

MATHEMATICAL MODELING OF MULTI PENDU-LUM SYSTEM
The formulation of a nonlinear triple pendulum chaotic system is similar to a double-pendulum system. For simplicity and to limit usage of the variables in mathematical formulation, the construction of differential equations of a double pendulum system is demonstrated below. Figure 2 exhibits a basic double pendulum pictorially.
The expressions of potential (P ) and kinetic (K) energies, as mentioned below, are obtained by analyzing position relations.
Later, Euler-Lagrange condition d dt ( ∂L ∂θ ) − ∂L ∂θ = 0 is applied, where L = K − P and Thereafter, substituting L into above mentioned Euler-Lagrange equation and solving the resultant equation for θ 1 and θ 2 , two second order differential equations are obtained.

Formulation of Compound Triple Pendulum
As stated above, the steps of mathematical formulation of a triple pendulum system is similar to the double pendulum system. In this section, an abstract representation of mathematical formulation of triple pendulum system is presented. The bars of a triple-pendulum have significant mass, so that it can be modeled as a compound pendulum. Damping factors are also included in the model to introduce higher degree of chaos and nonlinearity in the system. Each bar i is defined by a set of four parameters mentioned below. The position and velocity of the bars are defined by six system state variables, θ 1 , θ 2 , θ 3 ,θ 1 ,θ 2 ,θ 3 . The relevant governing equations to deduce these variable are given below.
x 2 = l 1 sinθ 1 + l 2 2 sinθ 2 (5) The magnitude of the velocity of each bar can be expressed as The translational and rotational kinetic energies, T KE i and RKE i , respectively, are depicted by The gravitational potential energy, GP E i , can be presented as Lagrangian of the system is expressed below.
Lagrange's equation can be defined as Rayleigh Dissipation Function, D, is described below.
Based on the above mentioned equations, a compound triple-pendulum model is numerically analyzed using MAT-LAB [25] employing ordinary differential equations (ODEs) used to describe random motions. The parameters and initial conditions of these ODEs are given in Table 1. For the analysis, numerical methods are utilized to solve a statespace model of differential equations, which are given in Appendix A. The numerical values corresponding to angular positions of the bars are obtained within a certain duration as per the predefined precision. This generates a chaotic map for an encryption module. The equations ofθ 1 ,θ 2 andθ 3 stated in Appendix A can be simplified as follows. θ 1 ,θ 2 andθ 3 are evaluated using differential equations by Later, θ are stored in a vector y, such that, i , ..., θ (N −1) i }, f or i = 1, 2, 3 and N = T ∆t Subsequently, y is phase wrapped in the range [0, 2π] (or [−π, π]) to achieve, It is to mention that state variablesθ 1 ,θ 2 andθ 3 are used to generate a one-to-one function F , such that, The Figure 3 presents a circular auto-correlation, estimated power of θ 3 with respect to its periodicity for periodic and nonperiodic trajectories. Periodic nature of circular autocorrelation signifies overall periodic nature of the trajectories and vice-versa. It can be observed from Figure 3(a) and Figure 3(b) that the power is concentrated around a few frequencies for periodic signals, whereas, power is distributed in the whole domain for aperiodic signals as shown in Figure 3(c) and Figure 3(d), respectively.
Fisher's G-statistic tests are also performed to further visualize similar properties of periodic and non-periodic trajectories, which are depicted in Figure 4. These tests, which are illustrated in Figure 4, are periodogram, bob's path traced and the time variation of angles. Periodogram is the power spectral density at each frequency of a bob. Bob's The numerical values obtained from periodicity test, circular auto-correlation and other analyses clearly differentiates parameters and initial values, which leads to periodic and aperiodic nature of the motion. Thus, by iterating through all possibles parameters emphasizing nonperiodicity in the selection, a set of keys are generated. In the following section, an implementation of our proposed triple pendulum system is presented to validate its correctness along with a study on its chaotic behavior. In this section, main constituents of our proposed cryptosystem, i.e. key generation and encryption-decryption methodology, are described in detail. The proposed triple pendulum system is implemented using MATLAB in order to validate correctness of the mathematical model presented in section 2. Employing initial conditions given in the Table  1, the phase wrapped angular displacement profiles ofθ 1 ,θ 2 andθ 3 are generated. It can be observed that the proposed system is chaotic in nature because of aperiodicity of angular displacements. Lyapunov exponents and bifurcation tests for all the key parameters are presented in Figures 5 and 6 to verify chaotic nature of our proposed system. The encryption scheme based on chaotic dynamic system presented in section 2 is validated by attractor profiling obtained using Lyapunov exponents and bifurcation diagrams. The chaotic nature of a dynamic system is estimated by the presence of positive exponents in the Lyapunov test, which implies exponential divergence of the system. It is to mention that chaotic systems do not synchronize with any other physical system in reality, although their synchronization conditions can be formulated mathematically iff all the initial conditions and parameters resemble exactly with the actual physical systems, which is only possible in an ideal scenario. Thus, two similar chaotic systems produce significantly different outputs, when initial conditions and parameters are marginally different. For estimating Lyapunov exponents [26] for an oscillating chaotic system, a 3D Lorenz equation 15 is formulated and is compared with different parameters of our proposed dynamic system. It can be observed from Figure 5 that our proposed triple pendulum based dynamic system fulfills Lyapunov criteria and can be considered as a chaotic system.

KEY
Thereafter, a bifurcation diagrams are generated for all the independent parameters m 1 , m 2 , m 3 , l 1 , l 2 , l 3 , k 2 and k 3 for θ 1 ,θ 1 , θ 2 ,θ 2 , θ 3 andθ 3 each. It is to mention that generally chaotic nature of systems depends on a single parameter and its bifurcation diagram is produced by changing the value of that particular parameter. Our proposed chaotic dynamic system has total 12 parameters constituting an entire encryption space, and eight parameters among them exhibit highly chaotic behavior. All the bifurcation diagrams illustrated in Figure 6 are generated by solvingθ using initial conditions of Table 1. Using Figure 6, range of each key values employed for encryption and decryption can be determined. It is to mention that in Figure 6, θ 1 andθ 1 , θ 2 andθ 2 , and θ 3 andθ 3 are indicated with green, red and blue colors, respectively.

Key Generation
The key, K, of proposed symmetric cryptosystem includes parameters, such as initial conditions, time duration, time step, the minimum value ofŷ, and . The is a mapping interval and can be expressed as = (ŷmax−ŷmin) Nc . There are total 21 variables constituting basic key structure shown below.
3 , m 1 , m 2 , m 3 , l 1 , l 2 , l 3 , I 1 , I 2 , I 3 , k 1 , k 2 , k 3 , g,ŷ min ,ŷ min / }  Table 2 presents a comparison of key size and key memory for various PQC algorithms. It can be observed that the key size generated by our proposed method is the least amongst all other PQCs. It can be seen that for certain specific parameters or initial conditions, motion of the bobs of a triple-pendulum exhibits periodic nature after a certain span of time. Hence, it becomes imperative to eliminate those parameters or initial conditions for which motion is periodic to preserve chaotic behavior of the system. Therefore, Fisher's g-statistic test [28], is employed to extract prominent period of the signal using statistical analysis on the spectrum of a signal. This test exploits periodic components of the signal derived from its periodogram, which is used to identify hidden periods (or frequencies) of a time series. This is helpful in identifying dominant periodic behavior in a series. The periodogram indicates relative occurrence of possible frequencies oscillating in between a given interval repeatedly. It estimates Power Spectral Density of a signal x L (n) of length L, which is defined below. Here, F s is the sampling frequency.
The computation of P xx (f ) can be performed only at a finite number of discrete frequency points given by Fisher's g−statistic is defined as the ratio of the maximum periodogram value (P xx (f k ) or I(ω k )) to the sum of all periodogram values of a signal.
where, I(ω k ) are periodogram values. Using the values of g, dominant periods of a signal are calculated. Thus, after removing the range of the parameters, in which a signal exhibits possible periodic behavior, remaining values of the parameters can be utilized to span key space. Further, based on the bifurcation diagrams, the strongest key may be chosen for encryption and decryption steps. Since bifurcation is a resource intensive process, there is a tradeoff between power and choosing a stronger key for an application. In the following subsection encryption and decryption methods are explained in detail.

Algorithm 1: Proposed encryption algorithm
Input:ŷ, P, N c , η Output: The approach discussed in this paper is to convert plain text of M characters into an ASCII format and map it to the intervals formulated using state variables of the proposed triple-pendulum system. Figure 7  proach. The initial conditions and parameters of different equations constitute a part of the private key. The differential equations are numerically integrated to get state variable θ 1 , θ 2 , θ 3 followed by phase wrapping in the range of [0, 2π] or [−π, π]. Later, employing Baptista-type method, an entire range of chaotic function [ŷ min ,ŷ max ] is partitioned into a number of intervals equal to the number of characters (N c ). Each character in the plain-text P is first mapped to a specific interval (k) and is stamped with a time point (i) randomly selected from this interval. A permutation map π(k) is employed to determine interval identifiers for each character's ASCII value. Proposed encryption scheme is  depicted in Algorithm 1. Here, η is a constant and C is cipher text.
In the decryption module, an interval, in which an encrypted value lies, is computed using the same symmetric key. By applying inverse permutation map (π −1 (k)), corresponding indices are converted back to clear-text (P ). The message can be decoded by convertingP into characters. Proposed decryption scheme is presented in Algorithm 2.
In addition to the plain text encryption, the proposed method can also be applied to images with RGB values ranging from 0 to 255. The parameter N c in Algorithm 1 can be set to 256 and a serialized image is fed as an input for image encryption. This algorithm can be extended for video encryption as well by treating each frame as an independent image. Our proposed encryption and decryption algorithms are demonstrated on three set of images. The original, encrypted and decrypted images are illustrated with their corresponding histograms presented in Table 3. The parameters of a key used for encryption and decryption are m 1 = 0.2944, m 2 = 0.8756, m 3 = 0.0947, l 1 = 0.508, l 2 = 0.254, l 3 = 0.127, k 1 = 0.005, k 2 = 0, k 3 = 0.0008, I 1 = 9.526 × 10 −3 , I 2 = 1.625 × 10 −3 , I 3 = 1.848 × 10 −4 , g = 9.81. Selection of these parameters for a key is accomplished using bifurcation diagram shown in Figure 6. Although, histograms of input images are vastly different, but histograms of encrypted images are similar in nature. This makes proposed scheme less vulnerable as compared to other methods, because it is hard to determine input just by using an encrypted histogram without knowing key. It is to mention that the proposed scheme has wide range of applicability.

Complexity Analysis
The computational complexity of the proposed scheme is described below. The information rate of the proposed cryptosystem is defined as the ratio of the size of plain-text, SZ pt , to the size of cipher-text, SZ ct , which is defined below.
The overall time complexity of the complete encryption and decryption methods is the sum of individual complexities mentioned above, which add upto O(N ). Therefore, it can be utilized in many applications efficiently to make them secure. Since, both time and space complexities of the proposed method are linear, it offers a very good scope for its parallelization to boost performance at hardware level as well. Due to its immunity to quantum computing based attacks, scalability and being computationally simple, our proposed method becomes a prominent candidate to provide much needed security to various wide range of applications, such as IoT based smart systems, high throughput low latency systems etc.

HARDWARE IMPLEMENTATION
The proposed design has been implemented using System Verilog HDL on Digilent Zed-Board having Xilinx Zynq-7 FPGA. Its synthesized netlist is generated by Synopsis Design Compiler (DC) employing SCL's 180nm design libraries. For simplicity and to validate the proposed algorithms, permutation map (π(k)) is fixed as an identity map and maximum three state variables are stored in a particular interval for each character during an encryption phase. As a result, it is required to search over total number of characters, N c , for an interval during decryption cycle. For evaluating equation 14, its RHS expression is converted into a postfix format and the resultant postfix expression is stored in a ROM on an FPGA board. Later, this expression is evaluated using a stack-based postfix evaluation technique. The angle combinations of sinusoidal terms present in the expressions are cached in an LUT and are appropriately decoded while evaluating these expression. The overall block diagram of this scheme is presented in Figure 8 and its finite state machine is illustrated in Figure 9. The hardware design can be segregated into three main parts, viz. LUT and Memory, ALU and Control Unit. A brief description of these units are elaborated in the following subsections.

Look Up Table (LUT) and Memory
In the FPGA implementation, five LUTs and a stack memory are utilized for solving differential equations by evaluating postfix expressions, which depends on angle combinations presented in Table 4. These five LUTs are used to store Parameters, Angle Combinations, State Variables, Numeric Constants and Postfix Evaluations. Parameters represented in Table 1 are employed for the above mentioned purpose.
As it is mentioned earlier, in the implementation of postfix evaluations, RHS expressions in equation 14 are converted into postfix format. The resultant postfix expression constitutes numeric constants, state variables or parameters, operations and sinusoidal terms. Each of these terms is encoded to a 8-bit code and an entire postfix expression is stored in an LUT in the coded format. During postfix evaluation, these codes are decoded and an appropriate data value is fetched from a corresponding address. The 8-bit encoding format can be expressed as shown below. Type T/A Address/Op The mathematical model of triple pendulum system presented in the Appendix of this manuscript is parsed and evaluated using information presented in Table 5. Thereafter, stack memory is configured to execute encryption and decryption modules.  When a complex operation requires more resources than two immediate registers, then this operation is performed in two or more than two steps. In this operation, value stored in the second immediate register is pushed onto the stack and, corresponding memory location and program counter are updated. This process repeats until a complex operation is executed producing a correct output. This approach reduces resource utilization while performing a complex operation. Another advantage of using stack-based push-pop architecture is that it can be used for solving any differential equation expressed in the form of state-space equation. For this operation, only angle combinations and mnemonics stored in the stack need to be changed keeping hardware architecture identical for all the operations. The brief discussion on Arithmetic and Logic Unit (ALU) is presented in the following section.

Arithmetic and Logic Unit (ALU)
In the proposed design, an arithmetic and logical unit (ALU) consists of two addition, one multiplication, one exponentiation and one division modules. All these modules perform floating point operations in the standard IEEE-754 format. The datapath in the addition module is split into four stages. The clock frequency of this operation is fixed at 100 MHz to meet timing constraints of the FPGA employed in validation of the proposed design. The datapath in multiplication module is divided into five stages to achieve above mentioned clock frequency. Moreover, if required, the multiplication module can be configured to function in a pipelined mode. Exponentiation module evaluates value of a floating point input raised to an integer as an exponent. It instantiates multiplication module internally for the evaluation of an exponent. Datapath of division module is sliced into multiple stages to meet the target clock frequency of 100 MHz. However, the division operation requires significant clock cycles as compared to other operations, therefore, the design of proposed algorithms is optimized to keep the number of division operations as less as possible.

Control Unit
The control unit of the proposed design is essentially a finite state machine (FSM), which performs required tasks in a well-defined sequence. In order to implement it efficiently, the complete FSM is factored into smaller state machines hierarchically. The top level FSM serves as a controller for all the smaller FSMs. Detailed descriptions for these state machines are given below.
(i) Top Level State Machine: Figure 10(a) exhibits a simplified FSM of the top module. Description of each state is given below.
• DEFAULT: It is an initial state of FSM after reset.
• RECEIVE KEY: It receives encryption or decryption keys through USB or Ethernet interfaces. • EVALUATE EXPRESSION: It evaluates state-space expression using given initial conditions for a chaotic dynamic system. • MODIFY STATE VARIABLES: In this state, state variables are updated based on the previous state. It involves multiply and addition modules to perform updated operations. • OBTAIN CHAOTIC MAP: It evaluates a chaotic map through a linear combination of all state variables and calculates a linear combination of θ,θ and θ. It is to mention that θ corresponds to the chaotic map. Further, it calculates intervals, in which θ lies and adds it to corresponding address in LUT. • GENERATE CIPHERTEXT: It generates a ciphertext for a particular plaintext string using a generated chaotic map and utilizes LUT to convert plaintext to ciphertext. (ii) Evaluate State-Space Expression: Figure 10(b) exhibits an FSM of a state space solver module and its detailed description is presented below.
• DEFAULT: This is an initial state of FSM after reset.  forms an operation based on top two data values stored in a stack. • PUSH DATA TO STACK: It pushes data in a postfix expression or result of an ALU operation onto the stack. It is to mention that the differentiating factor between encryption and decryption operations in Postfix Expression Evaluation FSM depends on postfix expressions, which are stored in postfix evaluation LUTs. Employing the above mentioned FSMs, encryption and decryption algorithms proposed in this paper are implemented and validated against various benchmarks. In the next section, implementation results of these methods on various platforms are compared and discussed in detail.

RESULTS AND ANALYSIS
In this section, we present hardware implementation results and relevant tests for the randomness quality of a chaotic map generated by the proposed approach.

FPGA and ASIC Implementation Results
The detailed analysis of the proposed encryption and decryption algorithms is presented in section 4 to validate their correctness and efficacy. Later, these methods are implemented on hardware using System Verilog and is synthesized using Xilinx Vivado [32]. It is to mention that the results obtained using hardware implementation of these algorithms match with their MATLAB based implementations accurately. Table 6 exhibits a detailed comparison and resource utilization of our hardware implementation with other prior art work, such as Adrián et al. [29], Pérez-Resa et al. [30] and two variants of Richard et al. [31] etc., reported in the literature. It can be observed that the proposed design utilizes 45.20% and 71% less resources as compared to chaos based symmetric streaming encryption methods [29] and [30], respectively. It also uses 56% and 10.35% less resources than the above mentioned two variants of format preserving encryption algorithm presented in Richard et al. [31], respectively. It is to mention that our proposed method exploits maximum hardware resources, memory and LUTs, in storing state variables only. Although it enables proposed design to be memory optimized, but most of the static power is consumed to store content in memory. Since FPGA is the target device, a few DSP slices (DSP48) are employed during synthesis of the proposed design, which enable efficient implementation of trigonometric functions.
It can be observed further that the power consumption of our proposed design is 186 mW. Its throughput and theoretical operating frequency are 2396.164 MBps and 628.14 MHz, respectively. It has the least power-delay product when compared with other designs, which indicates that our proposed design is energy efficient as well. Thus, the high throughput of our design along with a very high energy efficiency and very high strength against attacks make it a suitable candidate to be used in the wide range of electronics systems ranging from smart IoT devices to low latency high performance systems. Further, the proposed Fig. 11: Chip layout at 180nm Bulk CMOS technology node design is realized employing 180nm Bulk CMOS technology available with Semi-Conductor Lab, India. Table 7 presents actual physical area, power and resource utilization esti-   Fig. 12: Power profile of the proposed design at various operating frequencies (1KHz to 500MHz) mated using above mentioned technology node at 250MHz clock. The chip layout of the proposed design illustrated in Figure 11 is developed by using Electronic Design Automation (EDA) tool, IC Compiler, provided by Synopsys Inc. Similarly, the synthesized design netlist is generated by employing Design Complier provided by Synopsys Inc. It is to mention that all the design parameters exhibited in Table  7 are extracted through IC Compiler. In order to validate usage of our proposed design in various applications, its power profile is analyzed by varying operating frequency from 1KHz to 500 MHz, which is presented in Figure 12. The total power measured at a particular frequency is the sum of static, dynamic and leakage power. It can be also be observed in Figure 12 that the static power contributes significantly to the total power. Below 100 KHz, leakage power becomes comparable to the dynamic power, which is not recommended for reliable circuit performance at 180nm technology. Above 100 KHz, leakage power is not significant as compared to static and dynamic power. It is to further mention that the leakage power does not rise substantially at 500 MHz as well. This implies that our proposed design can be used reliably at more than 100 KHz to high operating frequencies at 180nm technology node. With the smaller technology nodes, the operating range is anticipated to be different.

Chaos Analysis for Security Estimation
In order to test randomness of a chaotic map generated in the proposed method, various statistical tests are performed. These statistical tests are generally employed to validate randomness in pseudo random-number generators. As we know, these chaotic maps are used to generate keys for encryption and decryption schemes. Therefore, the statistical tests can ensure whether the keys generated in our proposed scheme are ideally indistinguishable from any true random sequence or not. The statistical tests, which are conducted to support our claims, are described below.   the chaotic map generated during analysis and the corresponding results obtained are presented in Table 8 and Table 9, respectively. In the NIST test, our proposed chaotic generator is compared with two recently published methods described in [33] and [34] to test its randomness. In [33], a sine chaotification model is employed to generate 1-D chaotic map, whereas, [34] presents physically unclonable functions (PUF) based chaotic maps. The [33] and [34] are used so that our proposed method is compared fairly with widely used chaotic schemes. For Diehard test, only self-test is performed due to the unavailability of similar tests in the literature to the best of our knowledge. From Tables 8 and 9, it can be concluded that the proposed chaotic map generator performs well among all the tests. This is largely due to nonlinear dynamics of chaotic map. The outcome of these tests indicate that the proposed chaotic map is indistinguishable with respect to any other random sequence generators depicted in [33] and [34].

Test for Chaos
There are a few essential conditions, which need to be met by any chaos based cryptosystem. These conditions include ergodicity, sensitivity to parametric values and sensitivity to initial condition to be as unpredictable as possible. For completeness, these essential conditions are described below.
(i) Sensitivity to Parametric values: A small perturbation in one of the system parameters, for example m 1 , is enough to create two exponential diverging trajectories starting at the same initial point. This is reflected in Figure 13(a) and Figure 13(b) for the parameters given in Table 1. (ii) Sensitivity to Initial Condition: Two trajectories starting at two different but arbitrarily close initial points denoted by θ 1 diverge from each other at an exponential rate. This is illustrated in Figure 13(a) and Figure  13(c) for the initial conditions given in Table 1. (iii) Ergodicity: Ergodicity is the phase space exploration either uniformly or randomly by a chaotic system. Here, phase space is defined as a relationship between angular velocity, ω, and the angle of pendulum's bob, φ. The triple pendulum system exhibits ergodic nature because phase space is sparse and is not cluttered in any specific region. The phase space of the bottom bob of the proposed triple pendulum system illustrated in Figure 14 under conditions given in Table 1 exhibits a trajectory, which satisfies ergodicity criteria. This leads to a conclusion that a system under specific conditions can be considered ergodic. The proposed triple pendulum based cryptosystem holds above mentioned properties, which are clearly evident in Figure 14 and Figure 13. It is to mention that the map generated using proposed compound triple pendulum model possesses essential chaotic properties to be employed in a general cryptosystem.

Collision Test
Collision resistance is the property of cryptographic algorithms, which makes it difficult to find two inputs that give the same encrypted output. It is well known that finding collisions is computationally very hard. In this paper, it is demonstrated that the proposed algorithm is fully collision resistant. As it is discussed earlier, an entire range ofŷ are partitioned according to number of characters. For example, N c = 256, i.e. [ŷ min +k ,ŷ min +(k+1) ) for k = 0, 1, ..., 255, which are mapped to different intervals. In the proposed method, two different inputs having different characters are mapped to different intervals always. Thus, it can be considered as collision resistant.
Based on the experimental and analytical results, it can be emphasized that the proposed scheme is better as compared to any other chaos based PQC algorithms. Because of smaller key size, optimal area, high throughput and low power consumption, it can also be used efficiently to enhance security of IoT devices as well as any low latency high performance secure application.

CONCLUSION
The work presented in this paper discusses a novel symmetric key cryptography scheme based on a nonlinear triple pendulum chaotic map. The detailed analysis and standard tests of the proposed method classify it to be considered as a potential post quantum cryptography (PQC) algorithm. The proposed encryption scheme is compared with various other chaos based schemes over standard security parameters to prove its effectiveness. The quantum-safe property of this method is due to its innate chaotic nature. Also, the highly nonlinear and interdependent unpredictable nature of our proposed scheme makes it difficult even for quantum computing based attacks to breach the security without complete knowledge of its key. It is also unbreakable practically with the partial knowledge of its key because of high sensitivity of chaotic maps to key values. An FPGA implementation of the proposed cryptosystem exhibit 45.64% less resource utilization, 33.60% less power consumption on an average and more than double throughput as compared to similar cryptosystem. The proposed cryptosystem is further implemented using 180nm Bulk CMOS technology occupying 0.20374 mm 2 die area and consuming 61.88 mW power at 250MHz at 180nm. It is shown that this system can operate from low (at least 100KHz) to high operating frequencies efficiently without showing any performance deterioration. The efficient area utilization of the proposed post quantum cryptosystem with high throughput at a very low power enables us to utilize it not only in the IoT based systems but also in the high performance applications to provide them desired strength against any malicious attack.