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A Pipelined Algorithm and Area-Efficient Architecture for Serial Real-Valued FFT

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posted on 01.02.2022, 03:14 by Fang HongJiFang HongJi
In this brief, we present a novel pipelined architecture for real-valued fast Fourier transform (RFFT), which is dedicated to processing serial input data.
An optimized algorithm of the stage division for RFFT is proposed to achieve an area-efficient RFFT computing structure with full hardware utilization.
A single path butterfly (SBF) and a real rotator are merged into one processing element (PE) in each stage except the last stage to save latency and hardware resources.

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Email Address of Submitting Author

11815025@zju.edu.cn

ORCID of Submitting Author

0000-0001-7440-4751

Submitting Author's Institution

Zhe Jiang University

Submitting Author's Country

China

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