A Pipelined Algorithm and Area-Efficient Architecture for Serial Real-Valued FFT

In this brief, we present a novel pipelined architecture for real-valued fast Fourier transform (RFFT), which is dedicated to processing serial input data.

An optimized algorithm of the stage division for RFFT is proposed to achieve an area-efficient RFFT computing structure with full hardware utilization.

A single path butterfly (SBF) and a real rotator are merged into one processing element (PE) in each stage except the last stage to save latency and hardware resources.