A Ratioed Driver Based True Full-Duplex Interconnect with On-Chip Background Calibration

In this paper, we propose a true full-duplex cell for space-constrained high-speed interconnects. The proposed interconnect can replace conventional simplex interconnects due to its ability to double the data rate with ease in PCB floor planning. The proposed ratioed driver-based self-interference (SI) cancellation technique uses an automatically adjustable on-chip background calibration which minimizes SI, to retrieve the far-end signal faithfully. The techniques used in the design relax linearity requirements and reduce power consumption for the transceiver. The SI cancellation is independent of the modulation format of the incoming signal from the far-end transmitter. Using the proposed technique reliable communication is possible between near-end and far-end transceivers without any synchronization. The proof-of-concept circuit has been designed and verified in a low-leakage 65 nm CMOS technology. The full-duplex nature of the transceiver can significantly reduce cross-talk in high-density interconnects compared to its simplex counterparts for the same throughput due to less stringent spacing requirements.