A Ten Level Inverter Scheme with Extended Linear Modulation Range Till Full Base Speed

In this work, a 10-level inverter scheme is presented to extend the linear modulation range (LMR) till full base speed operation of an induction motor (IM) drive. The increase in LMR is achieved by using a unique space vector pulse width modulation(SVPWM) technique such that no lower order harmonics (such as 5, 7, 11 and 13, etc.) are present in the phase voltage as compared to six-step mode operation of conventional hexagonal space vector structure (SVS) voltage source inverters. The proposed scheme can increase the peak phase fundamental voltage of the inverter from 0.577Vdc to 0.637Vdc (full base speed operation), irrespective of the load power factor (p.f), where Vdc is the DC link voltage of the inverter. The 10-level inverter structure is formed using a 2-level inverter and an H-bridge (HB) in cascade from one end and a floating capacitor-based 2-level inverter cascaded with an H-bridge from the other end to drive an open-end winding induction motor (OEWIM). All the HB capacitor voltages are balanced by using space vector redundancy. The claim of balancing the capacitor voltages throughout the whole modulation range is verified experimentally in this paper. Experimental results at different steady-state and transient conditions are shown to validate the proposed inverter scheme’s efficacy in increasing the LMR.


I. INTRODUCTION
I N last decade multilevel inverter(MLIs) have become very popular in high power applications namely variable speed drives, high voltage DC transmission, renewable energy and electric vehicles. It offers many advantages such as low harmonic distortion in voltage and current, low dv/dt across motor phase terminals, less bulky filter size, operation at low switching frequency etc . There are three popular MLI topologies -Neutral point clamp (NPC), Flying Capacitor (FC) and Cascaded H-Bridge (CHB) which are widely discussed in literature [1]- [3].
MLIs can also be realised by a dual inverter structure feeding an OEWIM where either end of stator terminals are connected to two separate inverters [4]- [8]. Among several dual inverter topologies, recently, the dual inverter with a single DC-link has become popular. Here the primary inverter is supplied by a DC link, and the secondary inverter is fed from a floating capacitor. This configuration aids in increasing the phase voltage levels with a reduced number of switches besides the benefit of reliability and fault-tolerant capability [4], [5], [8]. These two inverters together can generate a combined hexagonal multilevel space vector structure (SVS) of radius V dc similar to a 2-level inverter single hexagonal structure feeding the IM from one end using a DC-link voltage of V dc [4]- [6]. For any hexagonal SVS, the maximum peak phase fundamental voltage that can be attained from a DC link of V dc is 0.637V dc (correspond to the full base speed operation of the IM drive), when the inverter operates in six-step mode. But the generic SVPWM mode operation can achieve a peak phase fundamental of 0.577V dc in extreme linear modulation range (LMR). Here the maximum radius of the rotating voltage space vector (SV) is 0.866V dc that can be inscribed within the hexagonal SVS. Further increasing of the modulation range above 0.577V dc will result in all the lower order harmonics (predominantly 5 th , 7 th , 11 th and 13 th ) appearing in the motor phase voltage [9], [10]. These harmonic contents cause low frequency torque pulsations that may even break the motor shaft. Hence, these lower order harmonics need to be eliminated to operate the motor seamlessly till full base speed. In literature, different strategies are experimented in order to mitigate these lower order harmonics while increasing LMR [11]- [18]. A cascaded 7-level inverter comprising of a 3-level and HB presented in [12] increases the modulation range from 0.577V dc to only 0.6075V dc in case of unity power factor load (u.p.f) load. Another 7-level inverter topology presented in [13] is a cascade of 3-level T-type and HB extends the LMR till 0.615V dc for u.p.f load. In [11], a 5-level inverter scheme is presented, which adds a square-wave common-mode offset for increasing the LMR without any lower order harmonics till 0.63V dc . A hybrid T-type topology in [14] discusses about raising the LMR for a 9-level inverter for the first time. The topology employs an instantaneous common-mode offset adding technique for extending the LMR up to 0.6248V dc with u.p.f load. The 9-level inverter proposed in [15] uses a cascade structure of 3-level T-type and HB that can extend the LMR till peak phase fundamental 0.607V dc while supplying an u.p.f load. There are many polygonal voltage space vector structures used to eliminate the lower order harmonics from the motor phase -such as 12 sided polygon eliminates only 5 th and 7 th [16], 18 sided polygon eliminates 5 th , 7 th , 11 th and 13 th [17]. Higher the sides of the polygon, higher harmonics range are eliminated from the phase voltage [18]. But at the same time, capacitor balancing and size of the capacitor become critical to control in polygonal SVS.
In this work, a 10-level dual inverter scheme is investigated to eliminate all the lower order harmonics (5 th ,7 th ,11 th ,13 th , etc.) while extending the LMR from 0.577V dc to 0.637V dc V dc peak phase fundamental regardless of load power factor. The proposed inverter topology supplies an OEWIM where the primary side is a cascade of a 2-level inverter and HB while the secondary side is connected to a floating capacitor fed 2-level inverter cascaded with an HB. The proposed inverter structure will synthesize a hexagonal SVS of more than 9-levels, as discussed in section-III. Those extra levels will be switched in a unique way to extend the modulation range till full base speed without surpassing the maximum voltage SV amplitude of V dc along A,B,C phases at any time. All the capacitors in this topology can be balanced simultaneously and independently using the concept of opposing vector redundancy of a Space Vector Point (SVP). The proposal to balance the capacitors, even at extended modulation range (from 0.577V dc to 0.637V dc peak phase fundamental) for u.p.f load (since u.p.f is the worst case condition to charge balance all floating capacitors [15]) is explained thoroughly in section-IV along with experimental validation in section V.

II. POWER CIRCUIT TOPOLOGY
The schematic of the proposed 10-level inverter circuit configuration, fed from a single DC link, is shown in Fig.1. The power circuit is divided into two parts -primary inverter and secondary inverter, which are connected at either end of OEWIM. The primary and secondary inverters are comprised of a 2-level inverter and a floating capacitor HB. The primary 2-level inverter is connected to the DC link of voltage V dc while the secondary 2-level inverter is connected to a floating capacitor of voltage V dc /2 which is common for all the three phases. The primary side H-Bridge (HB-1) and the secondary

III. FORMATION OF SPACE VECTOR STRUCTURE
Since the proposed inverter structure is a cascade of primary 2-level, secondary 2-level, HB-1, and HB-2, the resultant SVS is generated by combining the respective SVSs of primary 2level, secondary 2-level, HB-1, and HB-2. The formation of the proposed combined SVS is illustrated in Fig.2 for 0 0 to 60 0 angle of the primary 2-level hexagon. Firstly, the secondary 2-level hexagonal SVS of radius V dc /2 is superimposed on the star marked locations of the primary 2-level SVS (which have a radius of V dc ) (see Fig.2, Step-1). In step-2 ( Fig.2), the starmarked locations from the generated 3-level SVS of radius V dc (formed by the combination of primary 2-level and secondary 2-level) are then overlapped by the 2-level HB-1 SVS of radius V dc /4. Consequently, the 2-level HB-2 SVS of radius V dc /8 is placed over the star marked locations of the 5-level SVS of radius V dc (formed by the combination of primary-2L, secondary-2L, and HB-1 within the original hexagon of radius V dc ) to generate the proposed 10-level SVS of radius more than V dc (Fig.2, Step-3). The 10th level vector points (VPs) that are realized by additions or subtractions of the pole voltage levels of primary 2-level, secondary 2-level, HB-1, and HB-2 in different ways provide the unique advantage towards performing PWM operation upto full base speed. The expanding of the LMR strictly relies on the optimum use of these 10 level space vector points (SVPs) so that all the capacitors can be balanced along with eliminating the lower order harmonics from phase voltage. The representation of the primary 2-level, secondary 2-level, HB-1, and HB-2 output voltages in SV sense are given by (4)- (8).
Step 1 Step 2 Step 3  shows sector-1 (0 0 to 60 0 ) of the resultant combined SVS of the proposed inverter scheme. The line XW of triangle ∆OXW represents the 9-level operation boundary of the proposed SVS. The maximum LMR during 9-level (∆OXW ) operation of the inverter, is denoted by the inscribed dotted circular arc of radius OR = 0.866V dc (corresponding to peak phase fundamental = (2/3)*0.866V dc = 0.577V dc ). But to generate the maximum peak phase fundamental of 0.637V dc from a DC link of V dc , the voltage space vector reference for the inverter has to follow the dotted circular arc of radius OR = 0.955V dc ( = (3/2)*0.637V dc ). Since this circular arc resides in between 9-level (line XW ) and 10-level (line Y Z) SVS boundary, to increase LMR (from 0.577V dc to 0.6366V dc ), 10-level vectors need to switch along with 9level vectors. Here, the 10-level vectors are applied along the trajectory XABW so that the projection of voltage SV, along A,B,C axis during PWM operation will never V dc . But the applications of these 10-level VPs tend to discharge the HB2 V dc /8 capacitors [14]. The objective of the present work is to find out a strategy to regulate all the HB1, HB2, and secondary 2-level capacitors in such a way that peak phase fundamental of 0.637V dc is achieved. The following section discusses the capacitor balancing method of the inverter scheme.

IV. CAPACITOR BALANCING STRATEGY
All VPs of the proposed inverter SVS can be divided into three categories from a capacitor balancing point of view (see Fig.3). The Set-I VPs comprise those points generated by bypassing both the HBs, only composed of primary 2-level SV and secondary 2-level SV. The second set of VPs (Set-II) comprises primary 2-level, HB-1, and secondary 2-level while bypassing only HB-2. The Set-III VPs are formed by combining primary 2-level, HB-1, HB-2, and secondary 2level SVs. Hence it is conclusive that Set-I VPs do not affect C HB1 and C HB2 capacitors voltage other than disturbing only C sec−2L floating capacitor. Similarly Set-II VPs disturb C HB1 and C 2L capacitor voltages while C HB2 capacitors remain unaffected. However, the Set-III VPs affect all the capacitor voltages. All the C HB1 , C HB2 , and C 2L capacitors are chargebalanced by applying the concept of the opposite vector of

A. Capacitor Balancing for VPs up to 9-level
Till the 9-level operation of the inverter, any VP within the ∆OXZ can be switched in a PWM cycle to generate a reference vector. Let say, for instance, vector − − → OV (see Fig.5(a)) which is a set-III vector is switched in a PWM cycle. All the possible vector state redundancy for vector − − → OV is listed in Table- − → IJ (redundancy-6,7) need to apply to reach HB-2 vector − → JV . Hence, B-phase C HB1 capacitor can also be charged or discharged while using vector − − → XJ or − → IJ respectively. In the same way, opposite vector pair − − → OM and −−→ XM , − → ZI and − → XI will regulate the secondary-2L common capacitor C sec−2L based on the appropriate A-phase and B-phase current direction. Correspondingly, capacitor balancing for Set-I and Set-II VPs (which can be realized as a subset of Set-I VPs) can also be analyzed.

B. Capacitor Balancing for 10-level VPs
The proposed topology can increase the LMR till full base speed operation (peak phase fundamental of 0.637V dc ) by time averaging the 10-level vector points and 9-level vector points to generate a reference vector from the trapezoidal region (XABZ). Therefore, all lower order harmonics can be absent in the motor phase. But the switching of the 10-level VPs discharges HB2 capacitors. For example, in Fig.5 − → ZI and − → IX, it will discharge when vector − − → XG is applied since no opposite 2-level vector is available. The above discussion concludes that during extending the LMR to full base speed C HB2 capacitors discharge. Eventually, by supplying the required charge to balance C HB2 capacitors, C HB1 capacitors get discharged. The C HB1 capacitors need to charge back by using opposing HB-1 vectors which can be generated by utilizing such SVPs from secondary 2-level that have no redundancy. Hence, ultimately C sec−2L will discharge for all the 10-level VPs along AB line for u.p.f load operation. So, if C sec−2L voltage is regulated at full base speed operation, all other capacitor voltages can be balanced throughout the operation of Time Scale : 5ms/div Time Scale : 10ms/div Time Scale : 20ms/div 1.
2. respectively for the secondary 2-level capacitor in a sample time (n th sample). Here, E Dx 1 defines the discharging energy of C sec−2L for the 10-level VPs A, C, and D (x 1 = A, C, and D) which use the non-redundant secondary 2-level vector − − → XG, whereas E Dx 2 is defined for those 10-level VPs B, F, and E (x 2 = B, F, and E) where secondary 2-level vector − → ZL used. The charging of C sec−2L is possible in all 9-level VPs except X and Z (x 3 stands for those VPs) and it is defined as E Cx 3 . The C sec−2L capacitor can also get charging energy E Cx 1 ,x 2 , to some extent while generating the 10-level VPs by carrying b-phase current (along − → ZI or − → IX). The application time of each vector in a sample period is denoted by d x and β denotes the fraction of time for which C sec−2L capacitor either charges (β C ) or discharges (β D ) based on the capacitor voltage status while applying the specific VP. The total energy that is discharged (E total/D ) and charged (E total/C ) in sector one of the combined SVS are illustrated by eq.(11) and (12) respectively, where N is the total number of samples in a fundamental cycle and N/6 is samples in a sector.
It can be proved numerically that for sector-I of combined SVS (and hence for the full fundamental cycle, due to half wave and 3φ symmetry), total discharging energy E total/D of C sec−2L capacitor to generate 10-level VPs would be equal to the total charging (E total/C ) done during generation of 9-level and 10-level VPs in case of u.p.f load (worst case condition of capacitor balancing) at extreme modulation range (peak phase fundamental 0.637V dc ). Hence all the capacitors in the proposed topology are balanced for any load power factor till full base speed operation (see Fig.3, radius OR " ) of the inverter. Since, PWM operation is extended till full base speed operation, motor phase voltages become totally free from lower order harmonics. The following section will illustrate experimental performance of the proposed topology.

RESULTS
The hardware prototype of the proposed work has been implemented in the lab, and the control logic is performed using a TMS320F28335 DSP synchronised with Spartan XC3S200 FPGA platform. Here, the DSP senses the capacitor voltages and line currents through unipolar and bipolar Analog to Digital Converters (ADC). The PWM signals from the DSP are then passed to FPGA along with capacitor charging condition and line current direction. FPGA will generate the switching signals for the gate driver based on the stored look up table. A dead time of 1.5 µs is inserted between the complementary switches. A 7.5 kW, 200V, four poles OEWIM is used to perform the experiments. The results are taken for open-loop V/f control, and closed-loop rotor field oriented control with the OEWIM. The inverter circuit has used SKM100GB12T4 and IRF240N as power switches. Throughout the experiment, a 200V DC link voltage is being supplied to the inverter. Hence the nominal voltage of C sec−2L , C HB1 , C HB2 capacitors should be maintained at 100V, 50V and 25V respectively. The capacitors value can be determined for 5% ripple around nominal voltage using C = I peak /(f sw * δV ), where I peak is peak load current, f sw is 1.5 kHz and δV is permissible ripple in capacitor voltage. Though the designed value of C sec−2L , C HB1 , C HB2 are 0.66 mF, 1.33 mF and 2.66 mF respectively, the capacitor value used are 2.2 mF, 2.2 mF and 4.7 mF respectively based on the availability in the lab.

A. Inverter Operation till 9-level mode
The inverter will operate at 9-level mode till LMR of peak phase fundamental 0.577V dc . At different frequencies (see Fig.6), the motor is run in open loop V/f mode to obtain the inverter-motor combination's steady-state results. Fig.6(a)-(c) depict the motor phase voltage, HB2, HB1 and secondary 2level capacitor voltages at 10Hz, 30Hz and 45Hz, respectively. It can be observed that A-phase HB2, HB1 and C sec−2L a. 10Hz voltages are well settled at nominal values of 25V, 50V and 100V, respectively, during steady state operation at different frequencies. In Fig.7(a) and (b), primary 2-level, secondary 2level, HB1 and HB2 pole voltages for the inverter's A-phase are shown at 10Hz and 45Hz respectively.
The effect of sudden loading is presented in Fig.8(a) and (b) with a speed reversal from -40Hz to +40Hz under fieldoriented control (FOC). Here the machine current will increase suddenly due to sudden acceleration torque. The orthogonal motor current components I sd (magnetizing flux component) and I sq (torque component) have proper decoupling (see Fig.8(a)). It is seen from Fig.8(a) that I sd is kept constant throughout the speed transition, but I sq started increasing as soon as speed reversal command takes place and reaches a steady state after speed settled at +40Hz. In Fig.8(b), all the Aphase capacitors' voltage status are shown during the transient speed reversal. Here all the capacitor voltages are seen to be tightly maintained using the opposing vector redundancy in each PWM sample period. Fig.(8)-(c) and (d) show the functionality of the proposed capacitor balancing algorithm. At time instant t 1A , the A-phase HB-2 capacitor controller is switched off, and the capacitor is made to discharged by only applying the discharging logic from the SV redundancy (see Fig.8(c)). However, by switching on the controller at time instant t 2A , the capacitor is charged to its nominal value 25V. Similarly at t 3A , secondary capacitor C sec−2L controller is switched off and re-enabled at t 4A (see Fig.8(c)). So the capacitor voltage dropped and went back to the nominal value of 100V. In Fig.8(d), after disabling the controller at t 1B for A-phase HB-1 capacitor, it is reenabled at t 2B . At t 3B and t 4B disabling and re-enabling is done for secondary capacitor C sec−2L controller. These results also show the independent nature of control of all the Aphase capacitors of the inverter. It is true for other phases also. Moreover, discharging and charging one capacitor is not effecting the nominal values of other capacitors.
per phase. It can be verified from Fig.9(a) that all capacitors (see Fig.9(a)-traces (2), (3) and (4)) are regulated at nominal voltages during 50Hz u.p.f load operation. Hence the proposed capacitor balancing algorithm is working accordingly. Comparing the proposed inverter operation at 50Hz is made with conventional six-step mode operation as shown in Fig.9(b)-(g). In case of six-step mode operation, the α axis component V α and β axis component V β of phase voltages (see Fig.9(b) traces - (2) and (3)) yield hexagonal space vector structure as shown in Fig.9(c). Therefore all the lower order harmonics are present in phase voltage (see Fig.9(f)). Nevertheless, during the proposed 10-level mode of operation, the α axis component V α and β axis component V β of phase voltages (see Fig.9(d) traces - (2) and (3)) construct an almost circular Space Vector structure as shown in Fig.9(e). Hence all the lower order harmonics from phase voltage can be eradicated (see Fig.9(g)) by the proposed algorithm while increasing the peak phase fundamental to 0.637V dc .

VI. CONCLUSION
The present work discusses a cascaded 10-level inverter topology with extended LMR till full base speed operation (equivalent to 0.637V dc peak phase fundamental as seen in case of six-step mode operation of 2-level inverter with same DC link voltage). The proposed topology generates a multilevel SVS by combining the SVS of primary and secondary 2level structures, and two H-bridges. Till LMR of 0.577V dc , the inverter operates with 9-level hexagonal SVS. However, while increasing the LMR, it uses the 10-level VPs. The extension in fundamental voltage can be done for any load power factor. Since, for u.p.f load capacitor balancing is critical, focus in a.
d.   the paper is given to regulate all the capacitor voltages at u.p.f load. All the capacitors in this topology, can be balanced in each PWM cycle using the concept of opposing vector redundancy throughout whole modulation range. A detail analysis is provided in this regard. As utilizing 10-level VPs enable PWM operation, phase voltages become free from all the lower order harmonics at highest modulation range, 0.637V dc peak phase fundamental. Different steady states and dynamic performance results are showcased to validate effectiveness of the proposed experimental setup.