A Very Low Reference Spur Phase Offset Technique in Fractional-N Charge pump PLLs

Fractional-N charge pump phase locked loops (PLLs) suffer from the problem of increased in-band phase noise due to charge pump non-linearity caused by UP/DN chargepump current mismatch. Existing techniques that resolve this problem by introducing phase offset between reference and divide signals cause large reference spurs or increase jitter at PLL output. A very low reference spur phase offset technique is proposed in this work. It produces the lowest reference spurs compared to previously published works. A detailed comparison of the reference spurs caused by the different techniques to introduce phase offset is presented. Simulation results show that the reference spur level generated at the PLL output after applying the proposed technique is 26 dB lower than the existing techniques in the presence of 5% chargepump current mismatch.