Algorithm Level Error Detection in Low Voltage Systolic Array
- Mehdi Safarpour ,
- Reza Inanlou ,
- Olli Silven
Abstract
An energy efficient architecture for TPUs that is based on reduced
voltage operation. The errors are captured and corrected by utilizing
ABFT and hence aggressive voltage scaling is made possible.Feb 2022Published in IEEE Transactions on Circuits and Systems II: Express Briefs volume 69 issue 2 on pages 569-573. 10.1109/TCSII.2021.3094923 
