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Algorithm Level Error Detection in Low Voltage Systolic Array

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preprint
posted on 09.07.2021, 11:59 by Mehdi SafarpourMehdi Safarpour
An energy efficient architecture for TPUs that is based on reduced voltage operation. The errors are captured and corrected by utilizing ABFT and hence aggressive voltage scaling is made possible.

History

Email Address of Submitting Author

mehdi.safarpour@oulu.fi

Submitting Author's Institution

University of Oulu

Submitting Author's Country

Finland