Algorithm Level Error Detection in Low Voltage Systolic Array

Safarpour, Mehdi; Inanlou, Reza; Silven, Olli

doi:10.36227/techrxiv.14915100.v2

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Algorithm Level Error Detection in Low Voltage Systolic Array

preprint

posted on 2021-11-08, 22:04 authored by Mehdi SafarpourMehdi Safarpour, Reza Inanlou, Olli Silven

An energy efficient architecture for TPUs that is based on reduced voltage operation. The errors are captured and corrected by utilizing ABFT and hence aggressive voltage scaling is made possible.

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Email Address of Submitting Author

mehdi.safar12@gmail.com

Submitting Author's Institution

University of Oulu

Submitting Author's Country

Finland

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in IEEE Transactions on Circuits and Systems II: Express Briefs

Algorithm Level Error Detection in Low Voltage Systolic Array

Keywords

deep learning neural networks FPGA low voltage Tensor Processor Systolic energy efficient ABFT fault tolerance matrix multiplication convolution

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CC BY 4.0

Algorithm Level Error Detection in Low Voltage Systolic Array

History

Email Address of Submitting Author

Submitting Author's Institution

Submitting Author's Country

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Read the peer-reviewed publication

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Keywords

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