An Enhanced Ultra-High Gain Quasi Z-source Inverter

—This paper proposes an enhanced ultra-high gain quasi Z-source inverter (EUHG-qZSI). The proposed topology combines single switched inductor unit with single switched capacitor unit to achieve the ultra-high voltage gain. This single-stage inverter provides very high gain profile with limiting value of shoot-through duty ratio of 0.186. The numerator factor of its gain is also high. Thus, the suggested inverter achieves higher voltage gain than the existing ultra-high/high gain/two-switched topologies. It also retains desirable qualities such as common ground with input DC supply and continuous source-side current. The derivations of steady-state voltage gain, parameter values, current and voltage stresses of its components, input current ripple and losses in different components are given to analyze the operation and characteristics of proposed inverter. In this respect, various performance issues are compared with that of existing topologies to indicate its decent performances. Both simulation and experimental verifications of the suggested inverter are performed. The observations of both studies match well with the theoretical analysis.


I. INTRODUCTION
HE z-source/ quasi z-source inverter (ZSI/qZSI) [1,2] is recently focused in the research and development field of power electronics converter. This topology is mainly used in the context of solar or fuel energy conversion system or electric vehicle applications. Various merits of the single-stage inverter can be mentioned as, capability of both buck and boost operation during DC-AC voltage conversion, reliable in terms of immunity from false firing by electro-magnetic interference or permissible shoot-through state and distortion-free effect due to dead-time less switching signals. The qZSI is the advanced option over ZSI for lesser voltage stresses on different components, continuous source current and sharing of ground with input DC supply. Various topological developments are still going on with the main objective as more enhancement of voltage gain profile. The increased voltage gain with less shoot-This paragraph of the first footnote will contain the date on which you submitted your paper for review. It will also contain support information, including sponsor and financial support acknowledgment. For example, "This work was supported in part by the U.S. Department of Commerce under Grant BS123456." The next few paragraphs should contain the authors' current affiliations, including current address and e-mail. For example, F. A. Author is with the through period results in high modulation index of the inverter. This causes reduced harmonic contents in output AC-side voltage/current i.e. reduction of filtering requirements. The qZSI topologies can be categorized and discussed as, i) Coupled inductor type -This topology [3][4][5] changes voltage gain by adjusting turn ratio. But this converter is prone to spike in DC link voltage due to leakage inductance effect [6]. ii) Extended/enhanced boost type -The diode-assisted (DA) and capacitor-assisted (CA) topologies are used to improve the gain. The two topologies are regarded as extended boost configuration [7]. But the gain value is not satisfactory. Thus, enhanced boost qZSI (EB-qZSI) [8] is proposed to further improve the voltage gain. The passive components used in extended/enhanced boost type are more. iii) Switched inductor type -Switched inductor topology [9][10][11][12] is used in front-end instead of single inductor to improve the gain. Here, supply-side current is subjected to substantial amount of ripple. iv) Active switched capacitor type -This configuration [10] reduces inductor in the boosting network in expense of higher capacitor voltage stress. v) quasi switched type -The quasi-switched boost inverter (qSBI) [13] is also proposed to reduce number of passive components and also, it consists of single active power switch. But, more gain is desired. Therefore, switched-inductor qSBI (SL-qSBI) [14] is proposed in expense of significant ripple in input current. vi) High gain/boost type -Two high gain qSBI (HG-qSBI) are proposed in [15]. These do not share ground of its supply. An enhanced boost active-switched qZSI (EB-ASqZSI) [16] having common ground is proposed, whose voltage gain equals to HG-qSBI. In the progress of time, one high boost converter [17] is suggested to further improve the gain. It has moderate input current ripple. There is possibility of further improvement in boosting level. vii) Ultra-high gain -The very recent trend is the development of ultra-high gain qZSI. The multi-cell ultra-high gain topologies are proposed in [18]. But it uses more active switches in the impedance network, which can cause more switching losses. In [19], an ultra-high gain topology of qZSI family is proposed by taking combination of single switched inductor unit and active switched capacitor circuit for further improving the voltage gain also, it consists of lesser number of active switches in comparison to before mentioned multi-cell topology. Still, gain improvement is possible. In this paper, an enhanced ultra-high gain qZSI topology (EUHG-qZSI) is proposed by combining a switched inductor cell and an active switched capacitor cell, which is shown in Fig. 1. Here, the shoot-through duty ratio is limited within 0.186 and the numerator factor of its gain is 2 times of (1+shootthrough duty ratio). The proposed topology uses same numbers of passive elements (both inductor and capacitor) and active switches to that of the above said ultra-high gain qZSI [19]. Two diodes are only more in proposed inverter, but enhanced ultra-high gain profile is achieved.
Section II proposes operational modes of proposed EUHG-qZSI, derivation of its boosting factor, design of its parameters and small signal dynamic modeling. Voltage and current stresses of its different components, calculation of various losses and comparisons of various performances are presented in section III. The working of the proposed inverter through both simulation and experimental works are illustrated in section IV. Section V gives conclusions.

II. PROPOSED ENHANCED ULTRA-HIGH GAIN QZSI
The operation and its design, voltage boost expression of enhanced ultra-high gain quasi Z-source inverter (EUHG-qZSI) are discussed here.

A. Modes
Both shoot-through (ST) and non shoot-through (NST) states of its operation are presented along with dynamic equations.

1) ST mode
In ST mode, the circuit representation of proposed inverter is presented in Fig. 2(a). Here, the ON/OFF conditions of various switching devices are: S1-S7: ON; D1, D2 and D4: OFF (reversebiased); D3: ON (forward-biased). The conditions of passive components are: L1, L2 and C3: Charging; C1, C2 and C4: Discharging. The dynamic equations in ST mode are given in (1).

2) NST mode
In NST mode, the effective circuit diagram is shown in Fig.  2  ; 0;   Fig. 3 shows different waveforms of voltage and currents for various passive and active elements of proposed boosting network. There are two shoot-through states in a switching cycle. In the work of this paper, maximum constant boost control (MCBC) [20] pulse width modulation method is used. Here, the relationship between shoot-through duty ratio (D) and modulation index (M) is given by,

C. Voltage Gains
By applying Volt-Sec balance in the cases of inductors, the following equations are obtained as, From (4), the capacitor voltages are provided as, . ; .
The boosting gain is expressed from (5) as, Thus, boosting gain (B) of proposed impedance network is, The denominator of (7) gives the range of shoot-through duty ratio as, 0<D<0.186.
Here, the net voltage gain (G) is written as, The capacitor values are mathematically represented as,

III. PERFORMANCES
The voltage and current stresses and losses of different elements are derived and presented here.

A. Voltage and Current Stresses
The voltage and current stresses of various elements of proposed configuration are derived and presented in Table I.

B. Ripple in Input Current
The ripple in the supply-side current of proposed inverter is less due to presence of input-side indictor 'L1', which can be quantified as,

C. Comparisons of Various Performances
Plots of voltage gain comparisons are presented in Fig. 4. Various characteristics and features of proposed EUHG-qZSI are compared with that of existing high gain and ultra-high gain topologies in Table I

D. Computation of Losses
The loss calculations for different components are discussed separately as follows:

1) Losses in Inductors
Here, it is considered that the core losses are very small in comparison to that of conduction losses in inductors. The conduction losses in inductors are given by, In (18), 'rL1', 'rL2' and 'rL3' are series parasitic resistances of three inductors. In (12), RMS values of inductors (IL1(RMS), IL2(RMS), IL3(RMS)) are given by,

3) Losses in Diodes
The net loss (PD) in diodes consist of reverse recovery loss, loss due to forward voltage drop and conduction loss, which are mathematically written as, D rr fd oh P P P P = + + (16) In (16), .  I  I  I  I  P  V  I  I  I   I  I  I  I  P  r  I I I In (17), the average and RMS currents of different diodes are,

4) Losses in MOSFET switches
The average and RMS values of current through the power switch 'S7' are given by,

IV. VERIFICATIONS AND RESULTS
The working and performances of proposed EUHG-qZSI (parameters are given in Table II) are verified in both simulation and hardware platforms. These are described as follows:

A. Validation in Simulation Platform
The proposed EUHG-qZSI is realized in MATLAB-SIMULINK software platform. The responses of output-side load voltage, current and phase difference are given in Fig. 5 for load resistance and inductance of 50 Ω and 60 mH. Here, per phase load voltage is 110 V (r.m.s.) and corresponding current is 2.89 A (r.m.s.) having lag phase angle of 20.65 o . The output-side unfiltered voltage (per phase) of EUHG-qZSI is shown in Fig. 6. The FFT spectrums of the voltage is also shown in Fig. 6. In this context, various responses (inductor currents and capacitor voltages) of proposed impedance network for DC input voltage of 70 V are presented in Fig. 7. The MCBC PWM method is applied here.
In the study, the amplitude of phase voltage equals to 155.5 V (110 Vrms.) Thus, overall gain for the three-phase EUHG-qZSI is given by, 155.5/ (70/2) = 4.442. From this net gain, the 'M' is obtained and its value is 0.9918 p.u as per the expression in Table II for

B. Validation in Hardware Platform
The operations of proposed inverter are also done using hardware set up. The inverter is framed using power MOSFET (TOSHIBA: 2sk3878) switches. The TLP 250 chips are used to drive various switches. The required PWM signals are generated with the help of dsPIC 30F4011 controller. The proposed inverter is fed from a DC-power supply (ITECH: IT 6514C). Various practical waveforms are graphically traced by means of a digital storage oscilloscope (KEYSIGHT: DSOX2024A).
The DC supply voltage of the power source is fixed at a value of 70 V. Here, the resistor having value of 50 Ω and inductor of 60 mH are taken as AC load. Various obtained responses (per phase load voltage and current) of load-side variables are presented in Fig. 8(a). The respective value of voltage, current and phase difference are noticed as 110 V (r.m.s), 2.04A (r.m.s) and 20 o (lag). Measured unfiltered voltage (per phase) waveform is shown in Fig. 8(b). Fig. 8 In Fig. 10, the plots of obtained efficiency curves are provided at variable power outputs for different input supply voltages. Here, the efficiency values are reduced with the reduction of DC supply voltage. The reason is due to increased input current of impedance network (due to increment of boosting level), which causes relatively more conduction losses at comparatively lower input voltage condition. The power losses at various components are computed for the proposed EUHG-qZSI. The power condition is chosen as 630 W and DC supply voltage is 70 V. The loss distribution is presented in Fig. 11

V. CONCLUSION
One enhanced ultra-high gain quasi Z-source inverter is suggested in this paper. It combines single unit of switched inductor with an active switched capacitor unit. Various analyses on its working and performances are done in this paper. The upper limit of shoot-through duty ratio is found as 0.186, which is evident from the derived boosting factor. The numerator of the boosting gain is also reasonably high, which is 2(1+D). The number of passive components and active switches are similar to that of recent ultra-high gain power converter topology. Comparative features, characteristics and performances are presented in Table II to point its decent behaviour. The benefits of suggested single-stage inverter are mentioned as, i. It enhances voltage gain (Fig. 4) from that ultra-high / high boost configurations by reducing upper threshold of shootthrough duty ratio (0<D<0.186) and also, due to simultaneous increase of numerator of the boosting gain.   Thus, boosting factor is enhanced at upper range of modulation index, ii. Better output voltage quality i.e. reduction of harmonics can be achieved at a required voltage gain due to its operation at high range of modulation indices, iii. Ground sharing with input voltage supply is possible, iv. Insignificant amount of shoot-through current is due to suppression effect caused by input-side inductor.
The peak efficiency is found as 92.4%. Both responses of simulation and experimental studies show reasonable accuracy and also, the observations agree quite well with the analysis of the work. Thus, the real-time implementation of the proposed inverter is feasible.