Analytical Expressions for Voltage Controller Coefficients to Attain Desired Values of Total Harmonic Distortion and DC Link Voltage Undershoot in Power Factor Correction Rectifiers

The paper reveals analytical expressions linking the coefficients of PI controller, typically employed as voltage loop compensator of power factor correction rectifiers (PFCR), with two major performance merits (namely, total harmonic distortion (THD) of grid-side current and DC-link voltage deviation upon sudden load increase) and DC link capacitance to rated power ratio. The proposed methodology allows to concretize the commonly used "8–10Hz crossover frequency, 45 degree–70 degree phase margin" rule-of-thumb, typically utilized in application notes of commercial PFC controllers. Relations between voltage loop gain crossover frequency and phase margin as well as settling time of DC-link voltage response to a step load increase to the above mentioned performance merits are also derived in the paper. Provided design guidelines allow to precisely achieve desired values of the two mentioned performance merits and indicate the feasible range of possible DC link capacitance values. Proposed quantitative design guidelines are well-supported by experiments.


INTRODUCTION
Strict power quality requirements of modern grid codes force mains-interfacing converters to interchange current of predetermined shape with the utility [1], [2]. In case energy is drawn from the grid, power factor correction rectifiers (PFCR) (typically possessing boost topology [3]) are typically employed as grid-interfacing AC/DC converters [4]. As a result of unity power factor operation, instantaneous grid power contains both DC and double-grid-frequency pulsating components. On the other hand, the power drawn by the load fed by grid-connected power conversion system may be either pulsating component free or contain one with different characteristics than that of the grid.
Consequently, short-time energy storage element is typically required in order to cope with the sum of grid and load pulsating power components since DC power constituents sum up to zero in steady state to preserve energy balance [5]. Bulk (typically electrolytic) capacitors, connected across the DC link of the power conversion system are typically utilized for this purpose [6]. Pulsating power components, absorbed by the short-time energy storage element, generate DC link voltage ripple proportional to system power rating and inversely correlated to the DC link capacitance value [7] (with the exception of balanced three-phase system, where DC link-side pulsating power component is zero [8], [9]). Moreover, DC link voltage deviation from its nominal value caused by load variations is also inversely related to the DC link capacitance value. On the other hand, DC link voltage should remain bounded both in steady state and during transients to comply with power conversion system functionality and voltage rating of the DC link capacitor. This is why electrolytic capacitors are utilized in DC links of systems rated above several tens of watts. It should be emphasized that due to well-known weight, volume and reliability problems associated with electrolytic capacitors [10] - [12], electronic capacitors, capable of mimicking the operation of large capacitors while utilizing much smaller ones were recently suggested [13] - [15]. Nevertheless, even though an electronic capacitor is utilized, grid-side power quality and DC link voltage restrictions must be respected by the system. The trade-off between grid-side power quality (in terms of current THD) and DC link voltage deviation (typically in terms of undershoot) clearly pointed out in [16], forces PFCR DC link voltage control loop bandwidth to be restricted in order to keep the near unity grid-side power factor. It should be noted that most of existing practical designs begin with setting the PFCR DC link voltage control loop crossover frequency to a typical value of 8-10Hz and selecting 45-70 degrees phase margin.
However, these values are rather rules-of-thumb than clear design guidelines. Recently, the authors of [17] made an attempt to link grid-side current THD and DC link voltage overshoot with DC link voltage control loop compensator (typically PI or type-II) coefficients. However, the methodology was applied to grid-connected photovoltaic inverters, which unlikely to be exposed to step-like variation of DC-side power (as shown in [18], ramp-like power transients are more realistic to be assumed in such applications). Moreover, graphical solution was proposed in [17] and hence region of feasible solutions was not revealed.
It is interesting to note that while a variety of solutions aiming to weaken the above-mentioned trade-off was proposed in the literature [19] - [23], modern analog controllers still use classical PI or type-II compensation networks while digital controllers typically utilize some kind of gain scheduling to improve DC link voltage behavior during transients thus sacrificing the THD [24]. Thus, the inherent trade-off between grid-side power quality and DC link voltage deviation during load variation still exists.
In order to allow better understanding of the phenomena, several practical assumptions are made in the paper in order to establish clear analytical relations between grid-side current THD, DC link voltage overshoot and settling time following a step-like load change, amount of DC link capacitance utilized per kW rating, voltage loop crossover frequency and phase margin. It is shown that for a given THD, multiple values of DC link undershoot may be attained. However, region of feasible solutions is quite narrow and settling time is different for each selected performance merits pair.
The rest of the paper is organized as follows. PFCR essentials are briefly reviewed is Section II.
Steady-state and transient performances are discussed in Sections III and IV, respectively. Guidelines for voltage controller design based on revealed analytical expressions are given in Section V. Region of convergence is obtained in Section VI. Several practical examples are elaborated in Section VII and experimentally validated in Section VIII using a typical 500W bridge-PFCR prototype. The paper is concluded in Section IX. II.

POWER FACTOR CORRECTION RECTIFIER ESSENTIALS
A typical grid-connected AC/DC power conversion system is depicted in Fig. 1(a). The system consists of a PFCR, bulk DC link capacitance CDC and (optional) down-stream DC/DC converter (DSC). Corresponding functional diagram of the system is given in Fig. 1(b) [5]. In the following discussion, both converters are assumed ideal for simplicity (without loss of generality).   Typical PFCRs employ dual-loop controller structure, shown in Fig. 2 [17], with outer (voltage) loop regulating the DC link voltage to the set point value * via using a PI controller as voltage loop compensator. The controller calculates desired grid-side current magnitude * , which is then multiplied by unity-grid-voltage template sin(ωGt) to create grid-side current reference * , which is then tracked by inner (current) loop. Since only the voltage controller is of interest in this work, current loop is represented in Fig. 2 by its complementary sensitivity function Ti(s). Moreover, current loop bandwidth is typically much higher than grid frequency, hence may be assumed for frequencies up to ωG [18]. PFCR grid-side voltage and current are given by with ωG denoting grid frequency and vGM(t) and iGM(t) representing corresponding slow-varying (constant in steady-state) magnitudes. Instantaneous grid-side power is then with pGM(t) representing slow-varying (constant in steady-state) average power and ∆pG(t) signifying pulsating power component. Denoting slow-varying (constant in steady-state) load-side instantaneous power as pL(t) = vL(t)iL(t), DC-link power balance (cf. Fig. 1b) is given by Corresponding DC link energy and voltage are obtained as respectively, with (0) = √ 2 (0) . III.

STEADY-STATE PERFORMANCE
In steady state pGM(t) and pL(t) are constant Thus, (7) reduces to [25]   with * denoting DC link voltage set point (cf. Fig. 2). In typical cases, DC link voltage ripple magnitude (ΔVDC in (11)) is much smaller than DC link voltage set point. Therefore, (9) and (10) may be further simplified as Hence, steady-state operation point is a superposition of DC and double-grid-frequency terms, given by (cf. (1), (9) and (12)) The steady-state double-grid-frequency component of is obtained as and hence Steady-stage grid-side current is then obtained as (cf. Fig. 2 and (14)) Consequently, grid-side current THD is given by ( In practical systems, the following approximation holds [ (2) and (3), there is Perturbing the variables in (11) as and linearizing around the operation point (12) yields In practice, grid voltage magnitude variations are infrequent and rather slow, hence is further assumed. Corresponding small-signal representation of the system is depicted in Fig. 3. Load power-to-DC link voltage transfer function is then derived as Maximum DC link voltage deviation caused by the load step is then given by The worst case load step is the no-load-to-full load transition. Hence, for a PLR-rated system, (26) V.

CONTROLLER COEFFICIENTS DERIVATION
For a given desired performance merits pair (THD * , US * ), design equations set is given by (cf. (18), (23) and (29) Denoting the crossover frequency and phase margin as ωC and PM, respectively, the following holds   Moreover, taking into account the fact that in practice ωC << ωG and noticing that (cf. (32b)) ωn < ωC for ξn > 0.4, it may be concluded that 2 2 2 16 1.
where W{} signifies the Lambert-W function [26]. Coefficients of the voltage loop compensator (1) are then derived as (cf. (23b))   Once CDC/PLR value is decided on and one of the two performance merits (typically the THD * ) is imposed, the value of the other performance merit may be selected within the region given by (39).
It must be emphasized that selection of the second performance merit would affect the phase margin, loop gain crossover frequency and the y%-settling time % , obtained using (25)  On the other hand, vDC(t) should also remain below the rated voltage of DC link capacitors utilized, in order to prolong their lifetime. values, accurately predicted by (32). Simulated system response to zeroto -100% load step applied at 0.05s is shown in Fig. 9. It is well-evident that the desired performance merits pair, steady-state DC link voltage ripple magnitude and predicted 2%-settling time are accurately respected. In case 10ms hold-up time is required (mains half-cycle), the required capacitance raises to about 770μF/kW. This amount of DC link capacitance per kW rating imposes steady-state DC link voltage ripple magnitude of 5.2V (cf. (11), neglecting the DC link capacitor ESR). Corresponding region of feasible performance merit pairs (cf. (39)) is shown in Fig. 10. It may be concluded that for 0.1 undershoot, the system may attain THD theoretical minimum of 3.5%. It should be emphasized that even though (15) indicates that only the 3 rd harmonic contributes to grid current THD, in practical systems additional odd and even harmonics (of lower magnitudes) typically appear due to parameter non-idealities, circuit non-linearity, etc. Fig. 11  Consequently, in order to obtain grid-current THD of 5%, THD * should be set to 4.3% -4.5%.  Fig. 12(a) depicts the relation between 2%-settling time and US * for THD * = 4.5% while Fig. 12(b) presents 2%-settling time vs US * for THD * = 4.5%. It may be concluded that for a fixed THD * , rising US * yields settling time increase. On the other hand, 2% vs THD * plot possesses a certain minimum for a given US * . Bode diagrams of corresponding voltage loop gains is depicted in Fig. 13 with desired performance pair (THD * , US * ) = (0.045, 0.08) attaining the highest crossover frequency and lowest phase margin of (ωc, PM) = (2π•13.3rad/s, 42.5 o ) and desired performance pair (THD * , US * ) = (0.045, 0.116) attaining the lowest crossover frequency and highest phase margin of (ωc, PM) = (2π•9.29rad/s, 75.6 o ).

VIII. EXPERIMENTAL RESULTS
In order to experimentally verify the proposed methodology, a 500W boost converter-based PFCR was employed, as shown in Fig. 14. The control system was implemented digitally using TMS320F28335 DSP-based control card. Average current control at a fixed switching frequency of 150 kHz was adopted in the inner loop. The PFCR was fed by APS-7100 Gwinstek programmable AC power source set to operate as 50Hz, 230V mains and terminated by M9715B Maynuo DC electronic load set to operate in constant power mode. The total DC link capacitance value (including electronic load input capacitance) was CDC = 385μF, realizing CDC/PLR = 770μF/kW in order to match the Example in the preceding Section and the DC link voltage was regulated to * = 400V. Five sets of controller coefficients derived according to the five desired performance pairs indicated in Fig. 10  in current spectra, as predicted. Nevertheless, in case the value of the 3 rd harmonic only is taken into account for THD calculation, the outcomes closely follow the desired values. Measured settling times are indicated in Fig. 12, accurately matching corresponding analytical predictions.