Applying Two Equidistant Samples-based-PLL on Unbalanced Three-Phase Signals with DC Offsets
Delayed signal cancellation (DSC) is a popular method to separate the fundamental frequency positive- and negative-sequence components from unbalanced three-phase signals. Conventional DSC can separate the sequence components using a quarter-cycle delay. Fast DSC tools can achieve the same with less than a quarter-cycle delay. However, neither conventional nor fast DSC can handle DC offset without requiring additional delayed signals. This letter addresses this issue by proposing a modified DSC to estimate the sequence components with DC offset rejection and having arbitrarily fast convergence speed, i.e., low memory requirement. Two equidistant delayed samples of the measured grid voltages/currents are required to implement the proposed technique and can easily be applied in a phase-locked loop (PLL). Comparative experimental results demonstrate the suitability of the proposed approach over other DSC methods.