Asymmetrical ZVS-PWM Switched-Capacitor Based Half-Bridge DC-DC Converter With Switch Peak Voltage of Vin/2

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I. INTRODUCTION
In recent years, the increasing demand for power sources with high voltage and efficiency and low electromagnetic interference, together with light weight and reduced size, has led to the need for designers to develop new techniques or improve existing ones.Thus, dc-dc converters, which process high levels of power and energy, are currently one of the main subjects of focus in power electronics research.
The asymmetrical half-bridge dc-dc converter, initially presented by P. Imbertson and N. Mohan in [1] and studied in [2][3][4][5][6][7][8][9][10][11][12], presents high gain and high efficiency, soft commutation in the power semiconductors, small number of components.and is one of the most promising topologies in low-to-medium power applications.However, the voltage stresses on the switches are the same as the voltage in its power source, which hinders its implementation in applications that require high input voltages.For this reason, in applications where the input stage is as high as 750-1000 V, this converter is not always a suitable choice, since it would require the use of semiconductors with rated voltages of 1200 V.
Three-level isolated dc-dc converters [13][14][15][16] may solve this issue and are the most commonly used solutions for isolated dc-dc converter designs with these specifications.However, they use a larger number of components in the power stage, in addition to the need, in many applications, to control the voltages across the input capacitors, as this equalization does not occur spontaneously.This control requires the use of voltage sensors and additional circuitry, contributing to the increase in equipment cost and complexity.In addition, these topologies are not suitable for asymmetric operation, as this type of operation does not allow the equalization of the voltages in the capacitors.Even for symmetrical topologies, the distribution of voltages across the capacitors is sensitive to the modulation employed or to the imperfections of the gate signals of the switches.
The series asymmetrical half-bridge converter with voltage autobalance is proposed to reduce the power semiconductors voltage stress to half of the input voltage [17].Besides reducing the voltage across the switches, the proposed solution provides ZVS transition and natural voltage equalization across the input dividing voltage capacitors without control.
As a solution for the issue of high-voltage input, it is also possible to use commutation cells in a switched-capacitor, such as the ladder cell [18].However, the switched capacitor converter does not allow control of the load voltage by adjustments of the duty cycle D and this is its main disadvantage in relation to conventional converters.
Isolated dc-dc converters combining switched capacitor circuits and conventional isolated dc-dc topologies were proposed, aiming to reduce power switches voltage ratings and allow operation with wide voltage conversion range [19].
With the aim of combining the features of the asymmetrical half-bridge converter and the ladder-type commutation cell, this paper presents the asymmetrical half-bridge switched capacitor converter, as an alternative solution to the issue of high-voltage input, which preserves all the attributes of the original asymmetrical half-bridge converter, such as the output current and soft commutation, with a natural reduction in voltage stress of the components of the power stage to half the voltage value of the power source.
In the proposed converter, as will be shown below, the voltages of the input capacitors are naturally balanced, without the need for control, as usually occurs in isolated dcdc converters based on multi-level topologies.

II. PROPOSED CONVERTER
The power stage of the proposed converter shown in Fig. 1(a) is comprised of four power semiconductors S1, S2, S3 and S4, two fixed capacitors C1 and C2, a floating capacitor CS, a high frequency transformer T1, an output rectifier stage made up of diodes D1, D2, D3 and D4, and an output filter comprised of LO and CO.The load is represented by resistance RO.The inductances Lm and Lc represent, respectively, the magnetizing inductance of the transformer and the commutation inductance, usually formed by the leakage inductance of the transformer in addition to an external inductance.
The capacitor Cd is used to block the dc component of the voltage Vab, generated due to the asymmetry of the converter, as occurs in the conventional asymmetrical half bridge converter.The voltages across the capacitors C1, C2 and CS and the switches S1, S2, S3 and S4 are equal to half the voltage of the input source designated by Vin, this being the additional characteristic of this converter in relation to the conventional asymmetrical half-bridge converter.

III. OPERATION PRINCIPLES OF THE PROPOSED
CONVERTER In order to simplify the description of the operation and the analysis of the converter in the steady-state regime, the following simplifying hypotheses are adopted: 1) all power semiconductors, inductors and capacitors are considered ideal; 2) the voltages of capacitors are considered constant during a switching period; 3) the inductance LO of the output filter is considered sufficiently high so that its current can be considered constant during a period of operation; and 4) a single resistance RS, associated in series with the floating capacitor CS, represents all the conduction losses of the power semiconductors.
During a period of operation, the ideal converter has six operation stages which are described as follows.The topological stages are shown in Fig. 2 and the corresponding relevant waveforms are given in Fig. 3.

A. First stage of operation (t2 -t3)
The first stage of operation, which is shown in Fig. 2(a), starts at the moment when the current in the inductance Lc reaches a value equal to the output current reflected to the primary side of the transformer (I'o), thus enabling the switches S1 and S3 to conduct.In this operation stage, the voltage source Vin supplies energy to the converter and the load.

B. Second stage of operation (t3 -t4)
The second stage of operation, which is shown in Fig. 2(b), starts at the moment when S1 and S3 are gated off.The current in the commutation inductance (iLc) does not reverse its direction instantly.Thus, the current is conducted through the intrinsic diodes of the switches S2 and S4.All diodes of the output rectifier start to conduct and the voltage at its terminals becomes zero.

C. Third stage of operation (t4 -t5)
The third stage of operation, which is shown in Fig. 2(c), starts at the moment when iLc reaches a null value, reversing its direction.Thus, iLc is conducted through the channels of S2 and S4.All diodes of the output rectifier continue to conduct.

D. Fourth stage of operation (t5 -t6)
The fourth stage of operation, which is shown in Fig. 2(d), starts at the moment when iLc reaches a value equal to -I'o.In this time interval, the capacitor Cd supplies energy for the load.C2 and CS are connected in parallel, allowing the discharge of CS.This stage is concluded at the moment when the switches S2 and S4 are gated off and S1 and S3 are gated on.

E. Fifth stage of operation (t0 -t1)
The fifth stage of operation, which is shown in Fig. 2(e), starts at the moment when the switches S2 and S4 are gated off.As occurs in the second stage of operation, the current in the commutation inductance is not reversed instantly.Thus, all diodes of the output rectifier start to conduct and the converter does not provide energy transfer for the load.

F. Sixth stage of operation (t1 -t2)
The sixth stage of operation, which is shown in Fig. 2(f), starts at the moment when iLc reaches a null value, therefore reversing its direction and enabling the current, which up to this point is conducted by the intrinsic diodes of the switches S1 and S3, to flow through the channel of the MOSFETs.However, the load voltage remains equal to zero since iLc is lower than the absolute value of I'o

IV. THEORETICAL ANALYSIS OF THE PROPOSED CONVERTER
The average value of the load voltage Vo can be determined by analyzing the waveform of the voltage at the terminals of the output rectifier vret.In order to simplify the analysis, vret is reflected to the primary side of the transformer and its waveform is represented in Fig. 4.
On analyzing the topological stages presented in Fig. 2, the equations which define the voltages in the primary side of the transformer are determined.These are presented for the first and fourth stages of operation by expressions (1) and (2), respectively.For the other operating stages the voltage is null, as described in the previous section.(1) In Fig. 4 it can be noted that, for the time intervals represented by ta and tb, vret' is null, which leads to a reduction in the static gain of the converter.Thus, in order to the static gain to be determined it is necessary to determine the time intervals ta and tb.
On analyzing the waveforms of the voltage and the current on the commutation inductance (vLc and iLc), in Fig. 3, it can be observed that there is a voltage across Lc only during the time intervals represented by ta and tb.Thus, the duration of these time intervals can be defined through determining vLc.
Based on the analysis of the stages of operation, the values for vLc during the time intervals represented by ta and tb are defined by ( 3) and (4), respectively.
(1 ) 2 As previously defined, at the moment that iLc reaches the output current value reflected to the primary side of the transformer, the converter once again supplies energy to the load.Thus, the current in Lc at the moment when the third stage of operation is concluded is equal to -I'o.Having defined the values for ta and tb, the average value for the output voltage reflected to the primary is obtained through the following equation ' 1 (1 ) ( ) 22 Evaluating (7), we find the static gain given by   where n is the transformer turns ratio.Fig. 5 shows the converter static gain for different values of D as function of the normalized load current reflected to the transformer primary side, given by 4 .
To determine the current stresses in the capacitors of the switched-capacitor stage, the non-idealities of the transformer are neglected.Thus, it is considered that the current through commutation inductance is instantly reversed and the proposed converter operates in only two stages.
To simplify the analysis of the switched capacitor stage formed by S1-S4, C1, C2, Cs, Rs, and Vin, a current source with a current equal to o I  is connected at the terminals ab.During the first stage of operation, shown in Fig. 6(b), the instantaneous currents in the capacitors C1, C2 and CS are given by ( 10), ( 11) and ( 12), respectively.
During the second stage of operation, the above mentioned currents are given by ( 13), ( 14) and ( 15), respectively.
Let us assume that C1 = C2 = CS = C. Thus, the time constant τ is given by 4 3 The resistance Rs is equal to twice the Rdson resistance of one of the switches, defined in the manufacturer's data sheet, for the junction temperature provided in the dimensioning of the converter's power stage.Using (10), ( 11), ( 12), ( 13), ( 14) and (15), the effective values of the normalized currents in C1, C2 and CS are found and represented in Fig. 7 as a function of the product fs τ , for D=0.45.
On analyzing the curves shown in Fig. 7, it can be noted that the effective value of the current in CS is higher than those in C1 and C2, regardless of the value of fsτ.It can also be observed that for values of fsτ higher than 0.2, the effective values for the currents in the capacitators practically remain constant and close to their minimum values.However, for values of fsτ below 0.2, the effective values of the currents increase exponentially, contributing to the elevation of the conduction loss.V. COMMUTATION ANALYSIS Due to the asymmetry of the converter, the currents in inductor Lc at the instant S2 and S4 are turned off is different from the instant S1 and S3 are turned off.These currents are given by ( 17) and ( 18), respectively.
The ZVS range depends on the energy stored in the inductor Lc at the instant of the commutation, to charge and discharge the commutation capacitors associated in parallel with the switches.Thus, the ZVS is not achieved if the necessary energy is not stored in Lc before the beginning of the commutation.Consequently, the limit load range with ZVS is imposed by the smallest current in Lc, that occurs at the instant the switches S2 and S4 are turned off.
Due to similarity in the analysis of the two commutations, in this study only the analysis for the commutation of switches S2 and S4 is described, since it is the more critical of the two.Before the start of the commutation, the current iLc circulates through switches S2 and S4 and the corresponding topological stage is given in Fig. 8(a), where VCs2 = VCs4 = 0 and VCs1 = VCs3 = Vin /2.

A. Linear stage (t0 -t0a)
At time t = t0 the semiconductors S2 and S4 are gated off and the linear stage of commutation begins.The capacitors CS2 and CS4 charge while CS1 and CS3 discharge with constant current and the respective voltages evolve linearly.This stage ends at time t = t0a when the voltage VCS4 becomes equal to VCd, that is the voltage across the capacitor Cd.This commutation stage is represented in Fig. 8(b).

B. Resonant stage (t0a -t0b)
At time t = t0a the resonant stage of commutation starts, represented by the topological stage shown in Fig. 8(c).During this time interval the voltage across the inductance Lm is null and there is some resonance between the inductance Lc and the commutation capacitance.This stage of commutation ends when VCS2 = VCS4 =Vin/2 and VCS1= VCS3 = 0.
In Fig. 9 the main waveforms for turn off of S2 and S4 are shown.After time t = t0b the diodes arranged in antiparallel with S1 and S3 start to conduct the current iLc.The corresponding topological stage is shown in Fig. 8(d).
At time t = t0c the semiconductors are enabled to conduct before the current iLc is reversed, so that ZVS is achieved.The dead time td2 must be longer than the commutation time tc2.

C. Duration of Commutation
The duration of the linear stage of the commutation of the semiconductors S2 and S4 is The normalized state plane trajectory is shown in Fig. 10, which represents the resonant stage of commutation, shown in Fig. 8(c).
The duration of the resonant time interval is   where The duration of the commutation is the sum of the time intervals tl2 and tr2 and is given by  In general, tr2  0 and can be neglected.

VI. EXPERIMENTAL RESULTS
In order to validate the theoretical analysis of the proposed topology, an experimental prototype was designed and built, as shown in Fig. 11, and its specifications are given in Table I.In the experimental prototype a voltage clamping circuit was included, comprised of a fast diode (Dg), a resistor (Rg) and a capacitor (Cg), as shown in Fig. 13.This clamping circuit is employed to limit the peaks in the voltage across the diodes D1, D2, D3 and D4 of the output rectifier, caused by the reverse recovery currents during the commutations.
The voltage clamping circuit allows part of the energy stored in the commutation inductor Lc to be transferred to the output filter capacitor CO, which contributes to increasing the efficiency of the converter.
The components employed in the clamping circuit, along with the other components used in the prototype, are given in Table II.The semiconductor used was a (SiC) MOSFET, with a rated drain-source voltage of 650 V.    Fig. 15 shows the experimental waveforms of voltages across the switches S1, S2, S3 and S4.It can be observed that the voltages across them are equal to 400 V, that is, half the value of the input voltage, which is 800 V.The main attribute of this converter in relation to the conventional asymmetrical halfbridge converter, which is the reduction in the voltage stresses on the components of the power stage, is then verified experimentally.It is also verified that the equalization of the voltages across the capacitors occur naturally, without any action of control.17 show that both switches also turn off with ZVS.These waveforms show that in the proposed converter, as in the conventional asymmetrical half-bridge converter, the switches operate with soft commutation.The minimum value for the processed power with soft commutation is dependent on the parameters of the converter design, as is the case for all other PWM converters with soft commutation.
The efficiency of the experimental prototype, for different power values, was measured with the aid of a Tektronix power analyzer (PA3000), and the resulting curve is shown in Fig. 18.The maximum efficiency obtained is equal to 93.6% for a power load of 1 kW.The aim of building the prototype was to demonstrate its functioning and validate the theoretical analysis and it was not optimized to reduce losses.The theoretical distribution of the losses is shown in Fig. 19, where it is noted that half of these losses occur in the diodes of the output rectifier stage.Therefore, the replacement of the full bridge rectifier with four diodes, by a midpoint rectifier with two diodes, should contribute to reduce losses and increase efficiency.It is also observed that these losses can be reduced with the use of a better material in the design and construction of the magnetic devices.

VII. CONCLUSIONS
A new isolated dc-dc converter topology, generated by the integration of the asymmetrical half-bridge dc-dc converter and the switched-capacitor ladder cell, for high input voltage operation with soft commutation has been proposed.The advantage of the proposed converter with respect to the conventional asymmetrical half-bridge dc-dc converter is the reduction of the voltage stress across the power switches to the half of the input dc bus voltage, enabling the utilization of lower voltage rating power semiconductors.Moreover, in contrast to the isolated three-level dc-dc converters, there is a natural balance of the voltages across the input voltage dividing capacitors, without the need for control.An experimental prototype has been designed, constructed and tested in the laboratory to verify the converter operation principle and the theoretical analysis results.The authors believe that the proposed converter, like the series asymmetrical half-bridge converter with voltage autobalance for high input-voltage introduced in [17], can be a competitive candidate for low-to-medium power and high input voltage applications.

Fig. 1 (
Fig. 1(b) shows the gate signals of the ideal switches, without the dead time, which will be included later in Section V, where the commutation analysis of the converter switches is made.The proposed converter operates with asymmetrical pulse-width modulation (PWM).The switches S1 and S3 are set to conduct during the time interval (0-DTS) and S2 and S4 are set to conduct during the complementary time interval (DTS-TS).The voltages across the capacitors C1, C2 and CS and the switches S1, S2, S3 and S4 are equal to half the voltage of the input source designated by Vin, this being the additional characteristic of this converter in relation to the conventional asymmetrical half-bridge converter.

Fig. 4 .
Fig. 4. Waveform of the voltage at the output terminals of the bridge rectifier reflected to the primary side of the transformer.

Fig. 5 .
Fig. 5. Static gain of the proposed converter as a function of o I for different

Fig. 6 .
Fig. 6.(a) Simplified representation of the converter.(b) Equivalent circuit for the first stage of operation.(c) Equivalent circuit for the second stage of operation.

Fig. 7 .
Fig. 7. Graphic representation of effective values of the currents in C1, C2 and CS, normalized in relation to '

Fig. 9 .
Fig. 9. Circuit waveforms for the commutation initiated at time t = t6, when S2 and S2 turn off.

Fig. 10 .
Fig. 10.Normalized state plane trajectory for the resonant stage of soft commutation.
previously mentioned, the dead time td2 must be longer than the time tc2.Thus, 22 dc tt  .

Fig. 14
Fig.14shows the experimental waveforms of the currents in the primary and secondary windings of the high frequency transformer of the converter, operating with a power of 1.4 kW and rated input and output voltages.

Fig. 14 .
Fig. 14.Current waveforms in the transformer primary and secondary windings.

Fig. 16
Fig.16shows the gate signals and the voltages across the switches S1 and S2 during turning off.It can be observed that both switches turn off with ZVS.The gate signals and the voltages across the switches S3 and S4 presented in Fig.17show that both switches also turn off with ZVS.

Fig. 18 .
Fig. 18.Efficiency of the experimental prototype of the proposed converter.

Fig. 19 .
Fig. 19.Theoretical distribution of losses in the converter power stage.

TABLE II PARAMETERS
OF EXPERIMENTAL PROTOTYPE.