Clock Offset Estimation for Systems with Asymmetric Packet Delays
This paper proposes a new clock offset estimation that mitigates unwanted link asymmetry for precise clock synchronization. The main contribution is to address the design issue of the IEEE 1588 standard precision time protocol (PTP), which estimates clock offset under the assumption that the delays of exchanged packets are symmetric. To mitigate the issue, we focus on the fact that PTP measures asymmetry variation through the derivatives of its timestamps with respect to the time step. By exploiting the measurement of the variation, the proposed approach defines the asymmetry in the form of a linear differential equation (LDE) and leverages the LDE to define and exclude asymmetry-induced errors. Additionally, we clearly derive the state transition of the asymmetry. Subsequently, we derive a novel state-space model from our approach. The model describes PTP clock offset estimation perfectly, allowing optimal clock offset estimation. We verify the theoretical validity of the proposed method with real data. Our approach improves PTP accuracy by more than thousand times and achieves an accuracy at the level of tens to hundreds of nanoseconds on an asymmetric communication link. Our approach realizes an accuracy comparable to that of PTPv2, without the cost of specialized hardware.
Email Address of Submitting Authorymha@etri.re.kr
ORCID of Submitting Author0000-0002-7139-2852
Submitting Author's InstitutionElectronics and Telecommunications Research Institute (ETRI)
Submitting Author's Country
- Korea, Republic of (South Korea)