Compact FPGA Ring Oscillator Physical Unclonable Functions Circuits Based on Intertwined Programmable Delay Paths.pdf (1.17 MB)

Compact FPGA Ring Oscillator Physical Unclonable Functions Circuits Based on Intertwined Programmable Delay Paths

preprint

posted on 2021-08-02, 22:07 authored by Yangpingqing HuYangpingqing Hu, Yuqiu Jiang, Weizhong Wang

Compact FPGA based PUF extraction circuits based on intertwined programmable delay paths implemented on Xilinx FPGA.

History

Email Address of Submitting Author

Submitting Author's Institution

University of Wisconsin, Milwaukee

Submitting Author's Country

United States of America

Usage metrics

Categories

Components, Circuits, Devices and Systems

Keywords

FPGA Implementation Xilinx System Generator Matlab Simulink Co-simulation FPGA Designs Physical unclonable function Xilinx Zynq processing system Xilinx

Licence

Exports