DC Capacitor-Less Two-Terminal Unified Active Capacitor and Inductor

Flexible characteristics, tunable parameters, and improved power density are the desired attributes that have led to widespread research on active capacitors and inductors (ACI) in power conversion systems. However, the two-terminal realisation of ACI is challenging due to different trade-offs between power density, device stress, and reliability of the added components. Moreover, the requirement of handling second-harmonic ripple makes bulk electrolytic capacitors nearly indispensable in two-terminal ACIs. Thus, the scope of power density improvement becomes constrained. Hence, active capacitors requiring minimum or no bulk dc capacitance are seen as an attractive technology in recent literature. However, such solutions can mimic either inductive or capacitive behaviour with a single converter unit, restricting their adaptability across different applications. This limitation is addressed in this work with the proposed unified active capacitor and inductor (UACI), realised without any bulk dc capacitor. It emulates variable capacitance and inductance while offering a smooth transition from one characteristic to another. High effective impedance due to a small susceptance at the transition duty prevents undesirable current overshoot during the transition. A laboratory-scale prototype of the proposed ACI is fabricated, and the hardware is verified up to $\pm$450 VAR.

TCSC, TCR, STATCOM, etc. [1]. Electronic inductors employing single or double-switch boost converters, or asymmetric full bridge converters, are reported in the literature [2] for power factor correction in the diode bridge rectifiers. Of late, a series capacitor stacked H-bridge [3] and its inductive dual [4] have been proposed as two-terminal active capacitor and inductor, respectively, while utilising very low-power rated active devices. Fig. 1(a)-(d) depict examples of two-terminal active capacitors and inductors studied in the literature. Though the basic unit in all these topologies, being a single-phase H-bridge, requires a sizeable dc bus capacitance to handle second-harmonic ripple power [5], reduced capacitance dc bus configuration also exists [6] and is depicted in Fig. 1(b). Except from the conventional STATCOM ( Fig. 1(a)), other configurations shown in Fig. 1 emulate either capacitive or inductive characteristics. Therefore, applications requiring impedance changeover from capacitive to inductive or vice-versa [7] prefers H-bridge-based STATCOM despite having a large dc bus capacitance. Moreover, unified circuits, capable of emulating capacitive and inductive characteristics, are more adaptable due to their reconfigurability and interchangeability. Thus, it is desirable to have a configuration with (a) unified capacitive and inductive characteristics and (b) small dc bus capacitance.
In STATCOM-like applications, the dc bus is neither connected to any dc load nor supported by a dc source. Hence, the ripple in its dc bus voltage is not constrained by the dc load or source specifications [6]. A higher second-harmonic ripple across the dc bus is allowed as long as the input current THD remains within the limit [8]. Therefore, the dc bus capacitance requirement of single-phase converters in solid-state-variablecapacitor (SSVC) applications has been scrutinised in [6], [9]. The configuration of [6], shown in Fig. 1(b), though requires reduced dc bus capacitance, zero power factor (ZPF) lagging operation causes the over-stressing of the shared switching leg. Since the inductance emulation demands ZPF lagging operation, the use of this configuration is discussed for capacitance emulation only. The H-bridge topology in SSVC application is also studied in [8] to assess the feasibility of capacitance reduction by modifying the modulation strategy. It is shown that switching one of the H-bridge legs in a bus-clamped fashion [10] for half of the line cycle ensures better utilisation of the dc bus capacitor and brings down its capacitance from 1.25 to 1 per unit (pu). This method, too, works for capacitive emulation only and, thus, is not functionally a substitute for the conventional STATCOM. The capacitance utilisation is further improved in [11], where an SSVC topology is proposed with no dc-link capacitor at all. Fig. 1. Two-terminal active capacitors and inductors: implemented with (a) conventional STATCOM with bulk dc capacitor, (b) 3-leg converter with reduced bulk dc capacitor [6], and H-bridge with reduced apparent power for (c) active capacitor [3] and (d) active inductor [4].
However, its inability to mimic the inductive behaviour is one of its limitations, like the other SSVC topologies. This limitation is addressed in the present work by integrating the feature of inductive emulation to facilitate a smooth transition from one characteristic to another. The preliminary study on the proposed Unified Active Capacitor Inductor (UACI) topology and its operation is covered in [12]. The derivation of the topology, design considerations, a smooth start-up sequence, modelling, and closed-loop control design, discussed in the present paper, provide a comprehensive analytical framework for studying UACI. Experimental results demonstrate smooth start-up, mode transition, and steady-state behaviour. The major contributions of this work are: 1) A two-terminal solid-state variable inductor (SSVI) without a bulk dc capacitor. 2) Integrating SSVC and SSVI in a single circuit named unified active capacitor inductor (UACI). The same twoterminal circuit operates as an active inductor or an active capacitor with appropriate modulation. 3) A smooth transition from capacitive to inductive characteristics and vice-versa without any transient current overshoot. 4) Analysis of the operating modes and development of a dynamic model for closed-loop control. 5) A start-up sequence that minimises current transients during circuit energisation and operation. 6) Validation of UACI in simulation and experimental prototype. Before introducing the proposed circuits, the evolvement of UACI is discussed in Section II, followed by its comparison with single-phase STATCOM in Section III. Section IV explains its operating modes along with the corresponding equivalent circuits. Section V focuses on the criteria for passive element selections. Section VI presents the dynamic modelling; based on which the closed-loop control scheme is proposed. The simulation and experimental results in section VII validate the operation and control of the UACI.

A. Conventional H-Bridge STATCOM: Requirement of C dc
An H-Bridge STATCOM is traditionally controlled by maintaining a stiff dc-link voltage V dc [8]. Both the switching legs are switched at a high frequency with sinusoidal modulation.
Referring to Fig. 1(a), let us assume that the STATCOM draws a current i g when a voltage v g is applied across its ac terminals. Depending on the current reference, the circuit is controlled to behave as a capacitor or inductor between its ac terminals. When the STATCOM acts as a capacitor, v g and i g are given by (1) The corresponding modulation signal is given by, This results in a switching cycle averaged dc-link current This entire dc-link current (i dc ) flows into C dc , causing a second harmonic ripple voltage v 2 across it. The peak magnitude of this voltage ripple is In order to keep v 2 pk < k r per unit (pu) of V dc , the required value of C dc is calculated as At the rated condition, when I g = I g rated , the maximum value of the ac capacitance emulated by STATCOM is Thus, from (5) and (6), For the standard choice of 0.1 pu grid-side filter inductance [13], the lowest-order current harmonic (h = 3) remains within IEEE-519 specified limits (4% of I g rated ) if k r is chosen as 0.024. With the worst case of transients and voltage drop consideration, M is assumed to be 1, giving, Similarly, for the inductive behaviour of the STATCOM, Therefore, the emulated capacitance C e varies between 1 pu to 0 and the emulated inductance L e varies between 1 pu to ∞ for the current variation between I g rated to 0. It can be inferred from (6)-(8) that a dc bus capacitance (C dc ) of 20 pu is also required for 1 pu inductance emulation. Such a large dc bus capacitance requirement motivates the study of reduced-capacitance dc-link design for different applications [6], [8].

B. Reduced Capacitance DC-Link
As the dc bus of the STATCOM is not supported by any active dc power source like a battery, solar photovoltaic cell, fuel cell, etc., the ripple voltage restriction on the dc bus can be relaxed. However, the higher the ripple is, the worse the grid current THD becomes. For example, in the case of sinusoidal modulation at fundamental frequency ω, the presence of 2ω ripple in dc bus voltage gives rise to a third harmonic voltage across the ac terminals. If the modulation signal is modified to cancel this third harmonic voltage, it results in a 4ω ripple component in the dc-link current. Thus, the modulation-based harmonic compensation keeps adding even harmonics in the dc-link voltage while redistributing the ripple energy from low frequency to higher frequencies. Though shifting of ripple from low frequency to higher frequencies reduces the dc bus capacitance requirement, it does not ensure maximum utilisation of the dc bus capacitor. Following the steps elaborated in [14], the expression for the dc bus voltage v dc is found as where v pk is the maximum voltage across the dc bus capacitor C dc , and k is defined such that the ratio of the minimum energy stored by C dc to the maximum ripple energy is (k − 1)/2. Thus, for the minimum voltage v i across C dc , where, P pk is the peak ripple power input, and equals to V g I g . The graphical representation of (9), depicted in Fig. 2, gives the dc bus voltage profile for different values of k ≥ 1. The maximum utilisation of the dc capacitor is achieved [8] at k = 1, which makes v dc a rectified sine-wave with amplitude V pk = √ 2V g . Since v dc becomes a rectified sine-wave for k = 1, only a square-wave modulation [8] can ensure the desired input current THD. The flip side of this technique is that the control over the input current is lost. As a result, the converter behaves like an uncontrolled rectifier, the input current of which is decided by the small capacitance present across the dc bus. One standard method for control is to switch one of the H-bridge legs at high frequency and the other at line frequency, as typically done in totem pole PFCs [15]. A similar modulation approach is adopted in [8] for capacitive emulation where the emulated capacitance C e is related to the dc-link capacitance C dc and duty d of the high-frequency leg by C e = C dc d 2 . As the chosen dc-link capacitance decides C e , it is apparent that this method does not eliminate the dc-link capacitance.

C. DC Capacitor-Less Active Capacitor
The utilisation of the capacitor is further improved in [11] by using an ac capacitor instead of a dc capacitor. Fig. 3(a) shows the dc capacitor-less active capacitor circuit, called solid state variable capacitor (SSVC). The circuit configuration is similar to that shown in Fig. 1(b). However, the dc bus capacitor is eliminated, and an ac capacitor is provided across the poles of the main H-bridge to prevent the switching ripple injection into the grid current. The legs 'a' and 'b' are switched at the frequency of v g by square-wave modulation. Thus, the voltage across these legs becomes a folded sine wave, given by |v g |. Leg 'c' is switched at a high frequency to control the input current i g . However, unlike STATCOM, it can not emulate inductive characteristics.

D. Proposed Configuration for Active Inductor
In order to emulate inductance, the SSVC circuit is modified, as depicted in Fig. 3(b). This circuit emulates an active inductor named Solid State Variable Inductor (SSVI). An inductor L cb is connected between the poles of legs 'c' and 'b'. The modulation scheme remains unaltered from that of SSVC. Fig. 3(c) shows the gate signals for all three legs.
During the positive half-cycle of the input voltage (v g ), diagonal switches S 1 and S 2 are kept ON. The other pair of diagonal switches remain ON during the negative half-cycle of v g . Thus, pole 'b' gets connected to terminal 'N ' during v g > 0 and terminal 'P ' during v g < 0. If the switch S 5 is operated at a duty d T , ignoring the switching ripple, the average voltage across L cb is expressed as As the switching scheme connects In order to obtain a pure ac voltage of period T 0 across L cb , the following should be satisfied.
v cb T 0 = 0 where T 0 = 2π ω Therefore, from (11) and (12) This shows that leg 'c' is to be operated at a duty 0.5, emulating a fixed inductance instead of a variable one. If the duty of S 5 is  represented by d T p and d T n for v g > 0 and v g < 0, respectively, (13) gets modified to, Thus, from (11) and (12) v Combining (15) and (16), Therefore, from (17)- (19), Thus, a variable inductance L e is emulated in the range (L cb , L cb d 2 min ) when leg 'c' is operated at duty in the range (1, d min ). In order to unify capacitive and inductive characteristics together, the following configuration is proposed.

E. Proposed Unified ACI Emulation
Combining configurations of Fig. 3(a) and (b), unified ACI (UACI) configuration is obtained and depicted in Fig. 4(a). It consists of a capacitor C ca , connected between legs 'c' and 'a' and inductor L cb , connected between legs 'c' and 'b'. Similar to the expression for v cb in the previous subsection, v ca is found as The phasor diagram in Fig. 4(b) depicts the position of the voltage phasors V cb and V ca corresponding to the variables v cb and v ca , respectively. The current phasors corresponding to the current through individual passive elements, viz., L cb and C ca , are also shown along with the input voltage and current phasors (V g , I g ). It is to be noted that the input current i g is in phase with i L and i c for inductance emulation and in phase-opposition for capacitance emulation. 1) Duty Range for L e and C e Emulation: Considering the switching cycle averaged expressions of v ca and v cb , the emulated impedance Z e is calculated from the power balance in [12]. Thus, As L ca is designed to filter out the switching ripple, it is small enough to make the assumption 1 √ L ca C ca >> ω, which leads to the following simplification.
If α ω √ L cb C ca and d tr α 1+α , (23) indicates that the proposed circuit emulates capacitance and inductance for d < d tr Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply. and d > d tr , respectively. Fig. 5(a) shows the emulation characteristics, which move from capacitive to inductive as duty d varies. The transition duty (d tr ), at which the emulated characteristics change from capacitive to inductive, varies with different choices of α. In Fig. 5(a), emulated capacitive and inductive susceptances are expressed in per unit of the capacitive susceptance ωC ca and inductive susceptance 1/ωL cb , respectively. At d = d tr , the admittance becomes zero, assuring negligible transition current. The variation in the transition duty d tr with α is highlighted and can be read from the x-y plot of Fig. 5(a), which is shown separately in Fig. 5(b). The characteristics indicate the following: i) For lower values of α, a larger range of d is available for inductance emulation. ii) Similarly, for a higher value of α, the range of d, available for capacitance emulation, becomes larger. iii) An equal range of d is available for emulation of capacitance (d = 0 to 0.5) and inductance (d = 0.5 to 1) for α = 1.

2) Range and Resolution of Emulated Parameters:
The minimum value of emulated inductance L e corresponds to d = 1 and is found from (23) as Considering a deviation Δd in duty d around d tr , (23) is written as Substituting d tr in terms of α into (25), the emulated inductance for Δd > 0 is found as Similarly, the maximum value of emulated capacitance C e is obtained by substituting d = 0 in (23). Thus, For a deviation Δd < 0 around d tr , The emulated maximum inductance and minimum capacitance values are found by neglecting the higher order terms of Δd in (26) and (28), respectively, near d = d tr where Δd → 0. Therefore, the ranges of L e and C e are expressed as per unit of L cb and C ca as Fig. 6(a) and (b) depict per unit emulated capacitance and inductance as a function of duty for the range 0 ≤ d ≤ d tr and d tr ≤ d ≤ 1, respectively, with α being considered as a parameter. It shows that inductance emulation can emulate a higher inductance value, whereas, for capacitance emulation, the benefit is the flexibility to vary the emulated capacitance. The Thus, the proposed dc capacitor-less UACI can find applications in realising variable capacitors and inductors for reactive power compensation and tuning of resonant circuits. In UACI, an inductor with a smaller inductance is used to emulate a much larger inductance. Solid state tuning restorer (SSTR), proposed in [7] for the restoration of tuned condition in the 2ω-tuned LC filter, emulates either a small capacitance or a large inductance which comes in parallel with the physical inductor of the LC filter [7] for the fine adjustment of the tuning. Such applications can benefit from the proposed UACI.

III. COMPARISON WITH CONVENTIONAL STATCOM
The proposed UACI can be compared with a conventional single-phase STATCOM with respect to the following features.

A. DC Capacitor
Conventional single-phase STATCOM requires nearly 20 pu of DC bus capacitance, which is realised with electrolytic capacitors. As electrolytic capacitors are more failure prone, they often decide the lifetime of a converter [16]. In UACI, a bulk electrolytic capacitor is not present; however, an inductor is required, which can be designed as a reliable element to improve the converter's lifetime.

B. Modulation and Switching
In contrast to four switches in STATCOM, UACI requires six switches which may appear as a demerit. However, it is necessary to consider the modulation technique of the UACI to appreciate its benefits. In the conventional single-phase STATCOM, the H-bridge is modulated with sine-triangle modulation, requiring high switching frequency [17]. However, in the proposed UACI, the switching frequency of the basic H-bridge is the same as the line frequency. The added additional leg is switched at high frequency but with a constant duty (d) for the one half-cycle and its complementary duty (1 − d) for the other half-cycle of the line frequency. Thus, the optimal design allows the selection of low-speed switches for the basic H-bridge. The high-frequency leg (two switches) can be realised with wide bandgap devices with better switching characteristics, reduced or no reverse recovery, and reduced loss.

C. DC Bus Voltage Regulation
DC bus average voltage is required to be maintained at a constant level in conventional STATCOM. Though STATCOM exchanges only the reactive power with the grid, the losses in the switches and filters usually cause the dc bus voltage to fall from the desired level. Hence, an additional control loop is implemented to balance the active power to maintain the dc bus voltage. In the proposed topology, the dc bus voltage follows the profile of the rectified ac input. Hence, the additional control loop is not required to maintain the dc bus voltage.

D. Energy Storage by Passive Elements
The energy storage requirement by the major passive elements in UACI can be compared with the energy storage by the DC bus capacitor in single-phase STATCOM. One of the functional differences between a conventional STATCOM and the proposed UACI is that in STATCOM, the minimum emulated capacitive and inductive impedances are identical, which means if it emulates a minimum capacitive impedance of 1 pu, it also emulates a minimum inductive impedance of 1 pu, without exceeding the current limit. In the case of UACI, the minimum emulated capacitive and inductive impedances can be independently decided by choice of the capacitance C ca and the inductance L cb , respectively. For 1 pu inductive and capacitive impedance emulation, = ωL e,min = 1 pu (30) Therefore, ω 2 L e,min C e,max = 1 has to be satisfied. As C e,max and L e,min equal C ca and L cb , respectively, ω 2 L cb C ca = 1 to satisfy (30). However, in the proposed topology, the values of L cb and C ca are chosen such that ω 2 L cb C ca = α 2 . Thus, the minimum inductive and capacitive impedance emulated need not be identical in UACI for α = 1. It can be seen that, Thus, UACI is useful where the maximum inductive and capacitive VAR requirements are not equal, with the maximum inductive VAR being 1/α 2 times the maximum capacitive VAR. Hence, for Z cap,min = 1 pu and Z ind,min = α 2 pu, the energy handled by L cb is The maximum energy handled corresponding to the duty d = 1 isÊ where ωL e min = α 2 pu, V m =v g = √ 2V g = 1 pu, ω = 1 pu. Similarly, for C ca , the energy handled is The maximum energy corresponding to the duty d = 0 iŝ where 1/ωC ca = 1 pu. Thus, from (34) and (35), the maximum net energy handled by the major passive elements of UACI iŝ The ratio ofÊ STATCOM toÊ UACI is plotted in Fig. 7 for different values of α. The expression for the maximum energyÊ STATCOM , handled by the dc bus capacitor of the STATCOM, is found in the appendix. Three different cases corresponding to the average dc bus voltage V dc = V m , 1.2V m , and 1.3V m are considered for STATCOM to compare the ratio ofÊ STATCOM toÊ UACI . It can be noted that except for a small range of α, highlighted in Fig. 7, the ratio is greater than 1, indicating lesser energy handling requirement by the passive elements in UACI, compared to the dc bus capacitor in the single-phase STATCOM.

IV. OPERATION OF THE UACI
The operations of the UACI during steady-state and start-up are studied to evaluate the device stress and loss.

A. Steady-state
During steady-state, equivalent circuits pertaining to four intervals are considered, as depicted in Fig. 8. The intervals are elaborated in Table I for v g > 0, considering both i g > 0 and i g < 0. The voltages all three legs are subjected to are identical and given by, Thus, the voltage stresses for S 1 -S 6 are √ 2V g . The current paths through the different elements are shown in Fig. 8. For v g > 0, equivalent circuits are considered for all the feasible states of S 5 and S 6 . The current i g is either in the same phase or in the opposite phase with respect to i L and i c , depending on capacitance or inductance emulation, as   Fig. 4(b). From the equivalent circuits for v g > 0, it is found that the maximum current through switch S k : k = 1, 2, 5, 6 is |i L + i c |. For v g < 0, similar modes are repeated during i g > 0 and i g < 0, causing maximum current through switch S k : k = 3, 4, 5, 6 to be |i L + i c |. Thus, the maximum current stresses on all the switches are identical. However, the conduction loss distribution across the switches will be different as S 3 -S 4 and S 1 -S 2 do not carry any current during v g > 0 and v g < 0, respectively, whereas S 5 -S 6 conduct throughout the line cycle. From the switching cycle averaged expressions of v cb and v ca , given by (17) and (21), the current phasors for i L and i c are found as Therefore, the maximum voltage and current stresses on all the switches are equal at steady-state. Also, it is possible to limit the start-up transients by coordinating the turn-on instants of the low and high-frequency switching legs with respect to the input voltage v g , as described next.

B. Start-up
The goal of timing the turn-on of line-frequency and highfrequency gate pulses at the proper instant is to ensure minimum overshoot and distortion in the input current. Referring to Fig. 9(a), two start-up procedures are considered here: 1) Immediate enabling of leg 'c': Switching pulses to leg 'c' are enabled at t = T 0 /4 when v g reaches its negative zero-crossing. 2) Delayed enabling of leg 'c': Switching pulses to leg 'c' are enabled at the next zero-crossing of v g , marked as t = 3T 0 /4. Prior to enabling any of the switching legs, the anti-parallel diodes of legs 'a' and 'b' conduct and charge the snubber capacitor (C sn ) to √ 2V g . Either of the start-up begins when gate pulses to S 1 and S 2 are applied at the positive peak of v g , marked as instant t = 0 in Fig. 9(a). Fig. 9(b) shows the equivalent circuit before enabling the switching legs for v g > 0 and v g < 0. Current overshoot during start-up is alleviated if S 1 and S 2 are turned on at the positive peak of v g . Referring to Fig. 9(a) and (b), at instant t = T 0 /4, when v g is at its negative zero crossing, the other pair of diagonal switches S 3 and S 4 are turned on. As v Cca is in phase opposition with respect to v g , enabling leg 'c' at v g = 0 prevents current transients in leg 'c'. However, enabling leg 'c' at any subsequent v g = 0 does not have similar implications. The equivalent circuits during startup, corresponding to the delayed enabling of leg 'c', are shown in Fig. 9(c), (d), and (e). The interval corresponding to Fig. 9(e) causes an abrupt change in the current i c as both D 5 and D 6 (body diodes of S 5 and S 6 ) are OFF. This is reflected as a distortion in the input current i g as shown in Fig. 9(a) for delayed enabling. Unless S 5 and S 6 are enabled, in a complementary fashion, at each zero crossing of v g , distortion in i g is expected. Hence, the gate pulses for leg 'c' are recommended to be enabled at the next zero crossing immediately after enabling the low-frequency gate pulses. Section VII verifies the impact of immediate and delayed enabling of leg 'c' through simulation and experimental results. Apart from the transients and steady-state operation, switching ripples also impact the device stresses. Therefore, the design criteria for passive elements and evaluation of switching ripple are discussed in the next section.
V. COMPONENT DESIGN CRITERIA 1) Current Ripple: It has been found from (17) that the voltage across L cb is v cb = dv g . Neglecting the voltage drop across L g at frequency ω, it is accurate to assume,v cb v g for d = 1, wherex is the amplitude of any variable x, varying sinusoidally at frequency ω. For v g > 0, the switching frequency ripple components in the currents i L and i c are depicted in Fig. 10(a) and (b), respectively, with their slopes labelled. The peak of the switching cycle averaged current through L cb is given by,î Therefore, the peak of i L , along with the switching ripple, is Similarly, neglecting the voltage drop across L ca , the voltage Therefore, the peak voltage across C ca isv g , which occurs when d = 0. The peak of switching cycle averaged current through Taking the switching frequency ripple into account, the maximum current through C ca becomes The choice of L ca is decided by the maximum allowable peak current and switching current through the capacitor C ca .
2) Voltage Ripple: The switching frequency ripple current in i c results in ripple voltage across C ca . The peak switching frequency ripple voltage across C ca , corresponding tov g is given by,v However, the selection of C ca is not governed by the switching frequency ripple limit but by the maximum capacitance value to be emulated. Similarly, the selection of L cb depends on the required range of emulated inductance.
Let the maximum rated current of UACI be I * g . Therefore, for inductance emulation,v This signifies that, even for the minimum value of emulated inductance, the peak current should not exceed I * g . Thus, the minimum emulated inductance is L e,min =v g ωI * g (47) As, L e,min = L cb , the inductance of the physical inductor connected between pole 'c' and 'b' is found from (47). Similarly, for capacitance emulation, v g ωC e ≤ I * g , C e,max ≤ I * g ωv g (48) As C e,max = C ca , the capacitance of C ca is found from (48). The capacitor C ab carries the switching ripple present in either i c or i L based on the interval of operation, depicted through Fig. 8. In the absence of C ab , the converter injects switching harmonics into the grid. Hence, the capacitance of C ab is designed to filter the ripple in i L and i c (Fig. 10). This way, it ensures negligible switching harmonics in the grid current.

A. Dynamic Model
The dynamic model of UACI is developed from the equivalent circuits shown in Fig. 8. Referring to the steps of average modelling in [18], switching cycle averaged equations are written as follows.
where y Ts represents the switching cycle average of any variable y(t). Linearising the variables with respect to their steady-state amplitude, (49a)-(49e) can be written in state-space form as If i g is the output variable of interest, the output matrix is given by, C = 1 0 0 0 0 Therefore, the transfer function between duty d of leg 'c' to the input current i g becomes (53) The expressions for the numerator and denominator coefficients of the transfer function G p (s) are given in Table II. Based on the plant transfer function G p (s), the current mode controller is designed for closed-loop control of the input current i g to emulate desired capacitance or inductance.

B. Control Scheme 1) Open-Loop Control:
In open-loop control, the duty cycle d is calculated from the VAR reference as follows. The following equations decide the reference current peak. If the VAR consumption by UACI is Q * C capacitive, Similarly, for Q * L inductive VAR consumption by UACI, i) For d < d tr , it is found from (23) that emulated capacitance value and corresponding duty are ii) Similarly, for d > d tr , emulated inductance and corresponding duty are Thus, the required duties are found for both capacitance and inductance emulation, as C ca , L cb , and α are known. Fig. 11(a) shows the block diagram for implementing the open-loop control. Accurate performance of the UACI is obtained by closedloop control, implemented as described below.
2) Closed-Loop Control: Fig. 11(b) shows the schematic of closed-loop control, in which the amplitude of the measured current (Î g ) is controlled to match the amplitude of the reference current (Î * g ). The control schematic consists of the following components: i) SOGI QSG: Second-order generalised integrator (SOGI) based quadrature signal generator (QSG) is implemented to obtain two orthogonal signals v α − v β from the grid voltage v g . ii) Clarke transform: The pair of signals v α and v β is transformed into v d − v q and utilised in synchronous reference frame PLL to obtain the phase angle θ g of the grid voltage v g . The phase angle θ g is wrapped into the range [0, 2π). iii) Comparator: In comparator, θ g is compared with π such that g S 1 , g S 2 = 1, when θ g < π and g S 3 , g S 4 = 1, when θ g > π. iv) Amplitude detector: The amplitude (Î g ) of i g is calculated from measured i g and PLL angle θ g , using SOGI and Clarke transformation [19], [20]. v) Controller G c (s):Î g is compared with amplitude of the reference currentÎ * g , calculated from (54) and (55). The error is processed through the controller G c (s). vi) Modulator: The controller output is compared with a sawtooth carrier to generate the gate pulses for leg 'c'. The modulator and comparator are synchronised to generate gate pulses for all three legs. Fig. 12(a) shows the frequency response of the plant transfer function G p (s), derived in (53). Considering the reference current amplitude corresponding to Q * c = 150 VAR (Î * g = 1 A) and Q * L = 1500 VAR (Î * g = −10 A), frequency responses of G p (s) are shown. The presence of the second-harmonic component [21] in the calculated current amplitude (Î g ) necessitates below fundamental bandwidth control [20]. Therefore, an integral controller G c (s) = ( 1 2s ) is implemented to achieve a bandwidth of less than 10 Hz even at extreme loading conditions. Fig. 12(b) depicts corresponding loop-gain frequency responses.

VII. VERIFICATIONS AND RESULTS
For the circuit parameters given in Table III, hardware is fabricated to verify the operation and control of the proposed circuit. The photograph of the hardware set-up is shown in Fig. 13. The synchronisation of low-frequency gating pulses, types of start-up, and impedance emulation are validated by simulation and experimental results.  A. Gate Pulse Synchronisation 1) Line Frequency Gate Pulse: The gate pulses for legs 'a' and 'b' are synchronised with respect to the grid voltage. The waveforms of the gate pulse g S 1 for leg 'a' top switch, the grid voltage v g , and dc voltage v dc across 'P ' and 'N ', obtained in simulation and experiment, are shown in Fig. 14(a) and (b), respectively. The gate pulse g S 2 of the leg 'b' bottom switch is exactly same as g S 1 . The voltage v dc is folded grid voltage as seen in Fig. 14. 2) High-Frequency Gate Pulse: The gate pulse g S 5 for leg 'c' top switch is generated in synchronism with line-frequency gate pulses. The transition of g S 5 from d = 0.2 to d = (1 − 0.2) = 0.8 occurs exactly at the rising edge of g S 1 . Similarly, at the

B. Types of Start-up Considered
In order to verify the two start-up procedures, line-frequency and high-frequency switched legs are enabled in a timecoordinated manner. Fig. 16(a) and (b) depict simulation and experimental results corresponding to delayed enabling of leg 'c'. The input current shows distortion when v g = 0 and leg 'c' is disabled. Fig. 16(c) and (d) compare simulation and experimental results for the case when leg 'c' is enabled along with S 3 and S 4 at the zero crossing of v g . Unlike in the previous start-up, no significant distortion is seen in i g . The distorted part of the input current i g is highlighted in Fig. 16(a) and (b), and zoomed in on the simulation and experimental results of Fig. 16(e) and (f), respectively. Also, the waveforms of the current through L cb (i L ) and C ca (i c ) are shown together. The diode currents i D5 and i D6 in the simulation results of Fig. 16(e) indicate that there is a discontinuity in i c and consequently in i g , when the diode D 6 stops conducting, but D 5 is not in conducting state yet.  The experimental results in Fig. 16(f) captures i L , i c , and i g at that instant. The current waveforms captured in the experiment exhibit a close match with the simulation results.

C. Operation of UACI
The operation of UACI is verified by steady-state emulation of inductance and capacitance, dynamic change in emulated VAR, the transition from capacitive to inductive characteristics and vice versa, and grid voltage disturbance rejection. Fig.  17(a) and (b) are the waveforms corresponding to inductance emulation obtained in simulation and experiment, respectively. For an inductive reference current of 2 A pk or Q L = 300 VAR pk , inductance is emulated. Fig. 17(c) and (d) show the waveforms corresponding to capacitance emulation obtained in simulation and experiment, respectively. For a capacitive reference current of 2 A pk or Q c = 300 VAR pk , capacitance is emulated. Fig. 18(a) and (b) shows the major harmonic contents in the grid current and THD, measured using Precision Power Analyser Yokogawa WT5000, for capacitive and inductive emulation, respectively. The total harmonic distortion (THD) of the input current is found to be within 2.5% for V g = 110 V and i g = 4 A pk . THD is expected to be poor at lower current or VAR as the fundamental current is also small. Thus, the impact of the current harmonics on the grid voltage is captured by total demand distortion (TDD). The variation in the TDD with current amplitude is graphically represented in Fig. 18(c) for the input Fig. 19. Reference step-up and step-down from 1 A pk to 3 A pk and back to 1 A pk , respectively, for (a) and (b) capacitive emulation, and (c) and (d) inductive emulation. The ransition from (e) capacitive to inductive and (f) inductive to capacitive emulation for ±450 VAR which corresponds to 3 A pk current. voltage V g = 90 V, 110 V, and 130 V. For all the considered operating conditions, less than 4% TDD is achieved. Fig. 19(a) and (b) show the waveforms for change in capacitive reference from 1 A pk to 3 A pk and back to 1 A pk , respectively. Analogous changes in the inductive references are depicted in Fig. 19(c) and (d), respectively. Fig. 19(e) and (f) depict the experimental results highlighting the transition from capacitive to inductive characteristics and reverse, respectively. Scaled values of corresponding duty commands are accessed through DAC in the experiment and shown alongside. It is seen that when duty changes from below transition value (d < d tr ) to above transition value (d > d tr ), UACI starts drawing lagging current from leading current. Thus, its behaviour changes from capacitive to inductive. The transition takes four cycles based on the controller bandwidth. Table IV compares the incremental change in the emulated parameters obtained analytically, in simulation, and in experiment. It is to be noted that analytical results are close to simulation results when the circuit non-idealities are ignored. However, simulation results are comparable to that of experimental when circuit and operational non-idealities are considered. The average error between the experimental results and simulation results with non-idealities is less than 7%. Fig. 20(a) and (b) show closed-loop operation, which ensures that desired reactive current i g is drawn, following a change in  the grid voltage v g from 110 V RMS to 150 V RMS and reverse, respectively.

D. Efficiency
As the proposed UACI operates as a variable capacitor and inductor, the circuit should ideally exchange only reactive power. However, due to the switching losses in S 5 and S 6 , conduction losses in S 1 -S 6 , and in the passive elements, the efficiency figure of merit (η F OM ) is calculated as The experimental and analytical values of η F OM for different VAR and input voltage are depicted in Fig. 21. In analytical loss calculation, switching losses in S 5 and S 6 are calculated using gate charge method [22], taking the folded sinusoidal voltage and sinusoidal current waveforms of the switches into consideration. It is found that the device conduction loss contributes a significant portion of the total loss. The peak η F OM for capacitive and inductive emulation are 98.6% and 93.1%, respectively. Wide bandgap devices with reduced on-state voltage drop and an optimal inductor design with tape-wound amorphous or MPP powdered core can further reduce the losses.

VIII. CONCLUSION
A bulk dc capacitor-less two-terminal UACI is proposed, analysed, and experimentally validated. The circuit is capable of emulating capacitance in the range of 0 to 1 pu and inductance in the range of 1 pu to a larger value. The expressions for a practically achievable range of emulation are found considering the smallest change in duty possible. Different operating modes are elaborated to analyse the switch stress and derive the dynamic model. A stable closed-loop control design is accomplished with integral control, facilitating a smooth transition from capacitive to inductive characteristics and vice versa. Synchronised gate pulses, closed-loop operation as an inductor, capacitor, and transition between capacitive to inductive behaviour are verified in simulation and experiments. Incremental change in emulated parameters for a duty resolution of 0.05 is compared with analytical and simulated values. A recommended start-up sequence that minimises transient distortion in input current is outlined and verified through simulation and hardware experiments.

APPENDIX
In a single-phase STATCOM, which requires nearly 20 pu of dc bus capacitance C dc for emulating 1 pu of capacitance or inductance, the peak energy storage requirement for the dc bus capacitor is when the DC bus average value is assumed to be equal to the peak ac voltage. Usually, the average dc bus voltage V dc is kept higher than V m with a margin of 20% to 30%, requiring maximum stored energy to be 28.8V 2 m and 33.8V 2 m , respectively.