Deployment_of_Artificial_Intelligence_Models_into_Edge_Devices__A_Tutorial_Brief.pdf (426.41 kB)
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Deployment of Artificial Intelligence Models into Edge Devices: A Tutorial Brief

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posted on 2023-09-05, 14:42 authored by Marek ZylinskiMarek Zylinski, Amir Nassibi, Ildar Rakhmatulin, Adil Malik, Christos Papavassiliou, Danilo P. Mandic

Artificial intelligence (AI) on an edge device has enormous potential, including advanced signal filtering, event detection, optimization in communications and data compression, improving device performance, advanced on-chip process control, and enhancing energy efficiency. 

In this tutorial, we  provide a brief overview of AI deployment on edge devices, and we describe the process of building and deploying a neural network model on a digital edge device. The primary challenge when deploying an AI model in circuits is to fit the model within the constraints of the limited resources as the restricted memory capacity on IoT circuits and the finite computational power impose constraints on the utilization of deep neural networks on IoT. We addresses this issue by elucidating methods for optimizing neural network models. 

Part of the tutorial also covers the deployments of deep neural network into logic circuits, as significantly enhanced computational speed can be attained by transitioning the AI paradigm from neural networks to learning automata algorithms. This shift involves a move from arithmetic-based calculations to logic-based approaches. This transformation facilitates the deployment of AI onto Field-Programmable Gate Arrays (FPGAs).

The last part of the tutorial covers the emerging topic of in-memory computation of the multiply-accumulate operation. Transferring computations to analog memories has the potential to improve speed and energy efficiency compared to digital architectures, potentially achieving improvements of several orders of magnitude.

It is our hope that this tutorial will assist researchers and engineers to integrate AI models on  edge devices, facilitating rapid and reliable implementation.


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Imperial College London, Department of Electrical and Electronic Engineering

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  • United Kingdom