Derivation, Design and Simulation of the Zeta converter

—The purpose of this paper is to guide electrical engineering students from analysing basic DC-DC converter topologies to more advanced topologies. Textbooks and free online papers include the derivation of second order DC-DC topologies such as buck, boost and buck-boost, while fourth order such as the Zeta converter are not as readily available as open knowledge online. This paper provides a detailed derivation of the Zeta converter topology in continuous conduction mode (CCM), it presents an example of component sizing and verifies the design by simulation in LTspice. simulation, wide bandgap power semi- conductors, power module packaging and multi-physics finite element analysis.


I. INTRODUCTION
E LECTRICAL engineering students are typically introduced to the topic of switch mode power supplies through the analysis of basic second order DC-DC converter topologies such as the buck, boost and buck-boost converters. Derivation of these topologies are derived in detail available as online open-access sources [1]. However, generally for the fourth order DC-DC converter typesĆuk, Zeta and Single-Ended Primary-Inductor Converter (SEPIC) the detailed derivation of their operation is not as freely available. Fourth order DC-DC converters are mentioned in the most popular textbooks by Muhammad Rashid [2], Robert W. Erickson & Dragan Maksimovic [3] and Ned Mohan et al. [4], however they are not open access and derivations are not presented in detail either. Most of free online sources describing these fourth order DC-DC converter topologies most often focus on more advanced topics, such as state space control [5], comparison of total harmonic distortion [6] or design guidelines are given without much description on how to derive them [7]- [9]. This paper provides a detailed derivation of the Zeta converter, shown in Fig. 1, when operated in CCM. A design example is given and it is verified by simulation.

II. DERIVATION OF THE ZETA CONVERTER
In the following section instantaneous values of voltages and currents are denoted with lower case letters v and i, respectively, while capital letters V and I are used for average voltage and currents. The switch is turned on at t = 0 until t = DT s where T s is the switching period and D is the duty cycle. The voltage and current waveforms of inductor L 1 are shown in Fig. 2. For the converter operating in steady state and CCM, it is assumed that the current through the inductor begins and ends at the same value after an entire switching period. This is also known as the volt-second balance, meaning that the average of applied voltage on the inductor is equal to zero during a switching period, as given by Splitting the total switching period, T s , into two segments at which the switch is turned on and off Rearranging to get an expression for V C1 equals Similarly, the voltage and current waveforms of inductor L 2 are shown in Fig. 3. The volt-second balance of L 2 is calculated as By collecting terms this equals Again, this is rearranged for V C1 to equal By combining (1) and (2) This expression is then solved for the conversion ratio,

And by combining all terms
Alternatively, it may be solved for the duty cycle, D Thus for D in the range of 0 to 1, the Zeta converter is capable of both stepping the voltage up and down. If compared with the buck-boost orĆuk converter, the voltage output is noninverting, meaning that it has the same polarity as the input voltage, where the buck-boost andĆuk converters are inverting. Now (3) is rearranged to When inserting (5) to (1) we obtain an expression for the average voltage across the capacitor C 1 This information could also have been obtained by assessing the diagram in Fig. 1. When the converter is operating in steady state, the volt-second balance means that the average voltage across the inductors are zero. Thus, by applying Kirchoffs voltage law to the loop of L 1 , C 1 , L 2 and output V o , then the average voltage across the capacitor must be equal to the output V o .
Similarly, simply from assessing Fig. 1 and using the steady state assumption that the output capacitor C o is large enough to maintain a stable voltage, we may also conclude that As we are now reading information from the diagram, we can also conclude that in steady state the average current in the capacitors are zero, thus if we apply Kirchoffs current law, we obtain and For an ideal lossless DC-DC converter, all power, P , is transferred from the input to the output.
Thus, if we use (5), we obtain that However, we are not only concerned with the average values of the inductor current in L 1 and L 2 . It is just as important to choose a large enough inductance, to ensure that the inductor current ripple is adequately low. From Fig. 2 we may see that the inductor current ripple, ∆i L1 , can be expressed as. (5) and using that f s = 1/T s , where f s is the switching frequency, we obtain that From this equation we can see that to keep a low inductor current ripple, we may choose a large inductance or high switching frequency. The expression for inductor current ripple is also used to ensure that the converter operates in CCM. For the Zeta converter to always operate in CCM, it is required that the current is always above zero. The limit is when the inductor current just reaches zero at the very end of the switching period, t = T s , as shown in Fig. 4. Fig. 4: Inductor L 1 current at its CCM limit.
At the CCM limit, from geometrical considerations, we may read that the DC-value of the inductor current is I L1 = ∆i L1 2 . Thus, to ensure CCM we need that Substituting R o = V o /I o we get the following expression for the minimum size of inductance L 1 to ensure that it is operating in CCM.
Similarly for sizing of L 2 , we need an expression for the inductor current ripple of L 2 , denoted as ∆i L2 . Geometrically from Fig. 3, we see that The limit to ensure CCM for the current in inductor L 2 is shown Fig. 5. Fig. 5: Inductor L 2 current at its CCM limit.
Geometrically, the following equation must be fulfilled Inserting (7) and (12) to (13) equals Rearranging the equation to isolate L 2 , once again using that T s = 1/f s and R o = V o /I o gives the following equation for the minimum required inductance to ensure CCM operation.
In addition to the sizing of inductors and maximum allowable current ripple, it is also important to size the capacitors C 1 and C 2 for a maximum allowable voltage ripple, ∆V . To size the capacitors, we will utilize that the capacitance is defined as C = dQ dV , where Q is the electric charge. By rewriting to an average rate of change, we get ∆V = ∆Q C . The amount of charge is given as the integral of current ∆Q = i(t)dt. Now, for C 1 if we assume negligible current ripple, it is discharged by I L2 = I o during the switch on time, as shown in Fig. 6.
From the following observations we obtain the following equation Fig. 6: Current and voltage waveforms of capacitor C 1 By rearranging for the value of C 1 , we get that Typically, we will assign a requirement that the ripple of the capacitor voltage may not exceed some predetermined level, i.e. 1 or 5 % of its DC-value. Thus, the equation should be written as For sizing of C 2 we use geometrical approximations, as shown in Fig. 7. Similarly to the sizing of C 1 , we are interested in the change in charge, which is also the integration of current. The voltage and current waveforms of C 2 are shown in Fig. 7. Now, the charge which determines the voltage change of C 2 , is shown as the area A C2 . Geometrically we obtain that Collecting the terms and using (12) for ∆i L2 , we get that However, this only represents the charge. To size the capacitor we utilize C = ∆Q ∆V , where ∆Q = A C2 . For C 2 this gives This concludes the section, as we now have equations for the sizing of all passive components, L 1 , L 2 , C 1 and C 2 .

III. COMPONENT SIZING
The following section presents a simple Zeta converter design example. The input voltage of the converter is V d = 20V, while its output must be maintained at V o = 60V. The load resistance can be in a range of 50 to 100Ω. Since P = V 2 o Ro , we calculate the output power is in the range of 36 to 72 W.
As a design engineer, we have chosen that the switching frequency is f s = 50kHz, and that the maximum voltage ripple of both capacitors should be maximum 1% of the output voltage, thus ∆V C1 = ∆V C2 = 0.01 · V o = 0.6V. The converter must be operating in CCM.
First we calculate the duty cycle, D using (4) To size the inductor L 1 we use (11) as shown The worst case condition is when R o = 100Ω, which is equivalent to a low output current. Inserting numbers we obtain that L 1 must have a minimum value of Next is the sizing of inductor L 2 , given by (14) Once again, the worst case for this inductor, is when the output current is low i.e. closer to zero, which is the CCM limit. Thus, L 2 should have a minimum size of Now for the sizing of the capacitor C 1 we use (15) The worst condition for the capacitor voltage ripple is when the output current, I o , is high. For a fixed output voltage of V o = 60V, the highest output current occurs when the resistance is R o = 50Ω. This equals an output current of I o = Vo Ro = 60V 50Ω = 1.2A. Thus, the minimum capacitance of C 1 required, which ensures a voltage ripple of less than 0.6V, is calculated Similarly, using (16) for C 2 the minimum required capacitance This concludes the section, as all four passive components have been sized for operation in CCM. Note, that this example of a Zeta converter design procedure only had a single varying parameter. If necessary, see [10] for an example of a SEPIC converter with multiple design parameters being in a range.

IV. SIMULATION
In the following section, the circuit simulation software LTspice [11] is used to verify the converter design values calculated in Section III. The LTspice circuit schematic and the required SPICE directives used to specify the models for the switch and diode are shown in Fig. 8 The SPICE directives The devices in LTspice cannot be ideal, and thus they do not turn on/off instantly and they are neither perfect conductors or have infinite resistance in their on and off state, respectively. The switch and diode models are given in line 1 and 2. The on-resistance of both devices is defined as 1 mΩ and an offresistance of 10 MΩ. The gate threshold voltage of the switch is set at 0.5V, while the forward voltage of the diode is defined at 0.01V. Line 3 specifies a transient non-linear analysis stopping after 100ms, and that the circuit is solved without calculating initial conditions for any of the inductive or capacitive elements, meaning that all voltages and current start at zero.
The gate signal is defined as a voltage source pulse train, having a time period of T s = 1/f s = 1/50kHz = 20µs. For a duty cycle of D = 0.75, this means that the turn-on period is T on = T s · D = 15µs. This signal is then supplied to the switch.
The circuit is now ready for simulation. First we want to validate that the converter is operating on the limit of CCM, when the output current is at its lowest limit, equivalent to an output resistance of R o = 100Ω. Shown in Fig. 9 is the inductor current of both L 1 and L 2 . It is seen that the inductor currents reach zero just at the end of the switching period, as predicted by the design equations (11) and (14). Next, we want to verify that the voltage ripple of capacitors C 1 and C 2 is below the requirement of 0.6V, when the converter is operating at its maximum power output, which occurs at a power output of 72 W. Thus, the output load resistance is changed to R o = 50Ω the capacitors it is read that the voltage ripple is at the limit of the specified 0.6 V. Secondly, the approximated triangular waveform shape of v C1 (t) and sinusoidal-like shape of v C2 (t), which was shown in Fig. 6 and 7, are justified. This verifies the design equations of Section III and concludes this section.

V. CONCLUSION
A thorough derivation of fourth order DC-DC converter topologies is generally lacking in open access literature. This creates a knowledge gap for engineering students in moving from simple DC-DC topologies like buck, boost or buckboost toĆuk, SEPIC or Zeta. This paper provides a detailed derivation of the required equations to design a Zeta DC-DC converter topology for operation in CCM. Following the derivation, a simple design example is given for a case with variable load resistance. The converter design is verified by simulation in LTspice. The analytical equations show good compliance with the simulated waveforms.