Design Project Using 45nm CMOS Design Project Using 45nm CMOS

— this project is aimed to design two impedances matching network to let the source degeneration and common gate amplifier to achieve the ideal characteristic. In the source degeneration case as the resistance is so small, so we just use down converting matching network. As the source degeneration gives us a high resistance , we just match with a up converting network.


I. INTRODUCTION
The objective is to minimize the input noise figure and S11 and maximize the voltage gain for a source degeneration amplifier and a common gate amplifier operating at 10GHz from 1.2V supply voltage using 45nm CMOS gpdk. There are four characteristics should be follow. S11 at 10GHz should less than -40dB, voltage gain should more than 20dB, Noise figure should less than 2dB, DC power should less than 1mW.
In the source degeneration case, Lg and Ld are ideal induction, the other components are all non-ideal which means the other components may have noise in it and the value of these components vary in a small range. As we know that the source degeneration amplifier's gain is related to the impedance at source node and the impedance at drain node, so we may easily calculate the gain= -Ld/Ls and this may help us to select the value of Ld cause Ls is a non-ideal inductor and we should select Ld to match the Ls value.
In the common gate amplifier, Ld is an ideal inductor but the other components are non-ideal. As we know that the common gate gain= gm*rds, and Rin= gm*Ls/Cgs, we may know how to select the width and length of the mosfet to get the proper gm, rds and Cgs.

A. Review Stage
To finish the project, there are so many step should follow.
--First, analysis the circuit and build up the proper test bench, then us the DC analysis in cadence to let the nmos transistor works in saturation region.
--Second, knowing that in source degeneration case, we should use up converting matching network so we just use narrow band matching network to match the test port's 50 Ω to the impedance seen from gate. As we should let the whole circuit have low noise factor which means we should use less components to finish the matching.
--Third, then we just use ADE in cadence and use AC analysis to select the port 1 and port 2 to calculate the Sparameter.
--Fourth, we select the input port and output port to calculate the voltage gain.
--Fifth, change the test bench by deleting the two port and select the supple by adding noise then use ADE to see the noise factor.
--Sixth, as noise factor is related not only by noise at source, but also related to the amplifier's gain, so we just changed the value of inductor and mosfet's width and length to get the better value of noise factor.
--Seventh, the common gate amplifier has the same procedure as the source degeneration.

III. FINAL DESIGN RESULT
In source degeneration case: Fig. 1 Figure 1 to 7 shows the test bench for source degeneration and the value of S11, voltage gain and noise factor.
In common gate case: Fig. 8 Figure 8 to 14 shows the test bench for calculate S11, voltage gain and noise factor.

IV. DISCUSS
This project aimed to let us know how to design a LNA by knowing the characteristic of it. At first the professor told us to use non-ideal components to finish the design, which means the component cannot select the ideal value, so we just by fixed the inductor's value and then select the capacitor's value because the range of capacitor is larger than inductor. Then we also know that we should transform the central frequency to 10GHz and let the S11, noise factor have the optimize value at 10GHz.
At first we just want to calculate the noise factor, S11 and voltage gain in the same test bench, then we find that these three characteristic have trade off relationship because when we get a good S11 value we may not let the noise factor to become small at 10GHz which means we should use two test benches to get the S11 and noise factor.

V. CONCLUSION
In this project we know that we should know how to select the non-ideal component's value because we cannot use ideal components in real circuit, and we also know that there is trade off relationship between the characteristic of amplifier.

APPENDIX
The hand calculation that amplifier required, has already been written down on the A4 paper.