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Design of a Novel CMOS Voltage Divider.pdf (255.46 kB)

Design of a Novel CMOS Voltage Divider

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posted on 06.08.2021, 14:03 by Darshil PatelDarshil Patel
Passive linear voltage dividers are an essential part of the voltage sensing and detecting circuits. In this paper, a novel voltage divider is designed in 180nm CMOS technology and is validated with LTSpice simulations. The proposed circuit features very low steady current consumption and as a result, very little power dissipation around 200-300pW.

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Email Address of Submitting Author

darshilpatel7457@gmail.com

Submitting Author's Institution

Government Engineering College Gandhinagar

Submitting Author's Country

India