Design of a Novel CMOS Voltage Divider.pdf (255.46 kB)
Design of a Novel CMOS Voltage Divider
Passive linear voltage dividers are an essential part
of the voltage sensing and detecting circuits. In this paper, a novel
voltage divider is designed in 180nm CMOS technology and is
validated with LTSpice simulations. The proposed circuit features
very low steady current consumption and as a result, very little
power dissipation around 200-300pW.
History
Email Address of Submitting Author
darshilpatel7457@gmail.comSubmitting Author's Institution
Government Engineering College GandhinagarSubmitting Author's Country
- India