Design of a Strong-Arm Dynamic-Latch based comparator with high speed, low power and low offset for SAR-ADC

Comparators are utilised by Nyquist-rate and oversampling analog to digital converters (ADCs) to accomplish quantization and perhaps sampling. Thus, comparators have a  substantial effect on the speed and accuracy of ADCs. This study provides a revised design for a dynamic-latch-based comparator that achieves the lowest latency, maximum area-efficient realisation, reduced power dissipation, and low offset. The proposed circuit has been designed and simulated using GDPK  45 nm standard CMOS-Process to operate on 100 MHz clock, at  1.2V supply voltage. Design and simulation have been carried  out using CADENCE Virtuoso EDA tool. Compared to the  original design, the PDP was easily reduced by approximately  by 6% with offset voltage reduced by 8 mV without speed trade off.