Dynamic Offset Compensated Operational Amplifiers

The given work is devoted to designing and implementing different dynamic offset cancellation techniques for 50 nm technology CMOS operational amplifiers. The goal is to minimize or get rid of the effects of the offset voltage. Offset voltage exists in all differential amplifiers due to the fact that no pair of transistors can be fabricated with the same size, there is always a slight difference in their dimensions (length or width), this gives rise to an undesirable effect called offset, the value of offset voltage for cheap commercial amplifiers are in the range of 1 to 10 mV, de-spite the fact that this isn’t a significant value, due to the high gain of such amplifiers, this voltage is amplified by tens or hundreds of times, this results in clipping of the output signal and this further limits the amplifier’s maximum allowable input voltage within the given dynamic range, hence its of great importance to take this small voltage into consideration, low-offset amplifiers find applications in mixers, analog to digital converters, instrumentation devices, etc. In this thesis, by using two different techniques for removing offset voltage (chopping and auto-zeroing), five low offset operational amplifiers were designed. The implemented methods reduced the flicker noise by more than 457 times (from 9.4 nV/√Hz to 20 pV/√Hz) at 1 Hz. All the simulations were done using Cadence Virtuoso.

auto-zeroing, and chopping [5,[19][20][21][22][23][24]. at zero and low frequencies, offset, flicker noise and drift are the supreme fallacy sources in operational amplifiers. This is mainly applicable for op-amps designed with CMOS transistors. The succeeding topics are concerned with reducing flicker noise and lower offset, before explaining these techniques in detail, it is necessary to have a fundamental understanding of these issues [18][19][20][21][22][23][24]. Offset voltage occurs due to random unpredictabilities during manufacturing the transistors.
MOS transistors suffer from threshold voltage inconsistency since the threshold voltage is dependent on transistor's doping level and it is different for each transistor. Another common issue is mismatch between the transistors' lengths and widths. While flicker noise exists in lower frequencies, it is also known as (flicker or pink noise), this type of noise has a power spectral density of 1/f, the point at which this noise reduces to thermal noise is referred to as corner frequency. It is generally caused by the imperfections in the joint between the gate's silicon dioxide and the semiconductor substrate [5,18]. Flicker noise can be expressed as: whereis a technology dependent constant;is the transistor's width; is the transistor's length; − is the frequency; is the gate-oxide capacitance.
Trimming method is implemented during fabrication of the transistors to reduce transistor mismatch, it may also be reduced if larger size transistors are used (as in fig. 1.2) but this is not an effective solution because larger transistors need more area [4], which will lead to a higher cost, thus Polysilicon-resistor films are commonly used in typical CMOS processes because they are widely available and possess a high sheet resistance [17,18]. The laser-trimming apparatus is built from neodymium-doped yttrium-aluminum-garnet laser. The energy of the laser is soaked up by the pol-ysilicon film, this leads to localized crystallization of the material, hence that allows a very accurate reduction of the resistivity of the interest zone [17]. It is possible to obtain very low offset voltages using trimming, but this method does not reduce the flicker noise, hence other techniques (chopping and auto-zeroing) are needed to prevent this problem, they also compensate offset changes gradually as the amplifier parameters change due to again and temperature changes. driven by a clock at frequency fch, hence it will be transformed to a pulse voltage [9,[18][19][20]. Later, the modulated signal will be amplified along with the input offset. The second chopper acts as a demodulator, it demodulates the input signal to a DC voltage, and at the concurrently modulates the offset to the odd harmonics of clock frequency that will be removed by a low-pass filter [11,[18][19][20][21][22][23].
This results in a signal with no offset and flicker noise, these two components now exist at higher gives rise to chopper ripple [5], various methods exist to eliminate it (refer to fig. 1.8). One way is to use dummy switches that feed charge to the transistor switch, this in return gets rid of the existing charge. nonetheless, charge cannot be distributed equally between source and drain terminals, for that reason, this method is not very helpful. Another solution is using two transistors connected in parallel, this solution is handy with smaller input signals only, the last and most effective method is to use a fully differential circuit, this reduces the offset voltage by a factor of ten [5,18]. Apart from chopping, another major technique exists, it is called auto-zeroing, it is widely used to reduce offset voltage, this method is based on a sampling (discrete-time). It samples the voltage offset of the amplifier in the first clock pulse, and then subtracts it from the input signal in the second clock pulse [8,[12][13][14]18]. Three main topologies exist for auto-zeroing, which are: output offset storage, input offset storage and closed-loop offset cancellation with the help of a supplementary operational amplifier [18]. All the mentioned circuits use two non-overlapping clock signals (CK and CK) that are out of phase by 180 degrees, in other words when CK is logic one, CK should be logic zero and vise-versa, if both are on at the same time even for a very short moment, both of the inputs of amplifier inputs will be shorted, that will lead to undesired effects. The easiest method to realize an auto-zeroing amplifier is to put a capacitor at the amplifier's output, as illustrated in fig.   1.9, C1 capacitor stores the offset in one clock phase and compensates it in the next phase. At the first phase the amplifier works in its normal amplification mode, in other words F1, S1 and S4 switches are on while S2 and S3 are off. In the next phase, the amplifier is working in compensation mode, switches S1, F2 and S4 are off while S2 and S3 are on. This method is sometimes referred to as open loop offset cancellation.   When the clock signal F1 is high and F2 is low, the amplifier G1 works in amplification mode while G3 is in compensating mode, during the next clock cycle (F1 is low and F2 is high), G3 amplifies the input signal while G1 compensates for offset, this will lead to a continuous signal existence at the output, thus convenient for continuous-signal applications, additionally, this drastically reduces the flicker noise [12]. The only disadvantage of that method is occurrence of voltage spikes due to switching at the output (Vb1 and Vb2), it can be reduced by using active integrators instead of the capacitors [18]. An additional design exists (as shown in fig. 1.13) that solidly lessens chopper ripples, a combination of both auto-zeroing and chopping is used. That technique works because auto-zeroing reduces the ripples and the noise folding issue caused by auto-zeroing is solved by modulating to a larger frequency. A downside of that technique is reduction of signal to noise power because auto-zeroing's output is discrete.

Design of The Operational Amplifiers
The very first thing before attempting to reduce the offset is indeed implementing the operational amplifier, two operational amplifiers have to be designed (a typical single-output operational amplifier and a fully-differential operational amplifier), the single-output operational amplifier is used in auto-zeroing configurations, while the fully-differential operational amplifier is needed for the schemes that involve chopping, certain configurations may use two or more operational amplifiers, in such case, the other operational amplifiers are referred to as, auxiliary or supplementary op-amps, they serve the main operational amplifier. In this part, the schematic diagram of both of the operational amplifiers, their transient analysis results, magnitude and phase responses are provided.

Schematic of a single-output operational amplifier
A standard three-stage operational amplifier topology is chosen here, the first stage is differential amplifier, the next stage is gain-stage (common-source) followed by the last stage which is a buffer, buffer is used when the amplifier is used to drive large resistive or capacitive loads which is required in practice (as depicted in fig. 2.1).   is not considered (VOS = 0). The amplifier is driven by two differential input sources with an amplitude of 250 mV, having a DC component of 500 mV and the frequency is 1 kHz, the differential inputs are generated by using two voltage-dependent voltage sources, one with a gain of 1 and the other with a gain of -1.

Fig. 2.3. Test bench scheme of the single-ended op-amp
The transient analysis result is presented in fig. 2.4 below, the purple signal is the differential input, and the red signal is the resulting output, the amplification is visible, if desired, gain can be increased by modifying the feedback and the input resistors.   The transient analysis result is provided in fig. 2.11, the red signal is the input (has a peak-to-peak value of 196 mV), while the blue signal is the output signal (with a peak-to-peak value of 966 mV).
It may be concluded that the amplifier amplifies the signal correctly because 966/196 = 4.9, which is very close to 5 (the ideally calculated gain value). It can be seen that the fully-differential amplifier has a wider bandwidth, the bandwidth is 493 MHz, that is much larger in comparison with the previous op-amp but at the cost of its gain (47 dB) and its design complexity.

Design of Op-Amps with Dynamic Offset Cancellation
Offset voltage is a dominant error source for operational amplifiers especially at low frequencies, as mentioned earlier, it occurs due to mismatch in transistor sizes, offset is a very vital parameter for operational amplifiers that is used in various applications for instance, calibrating signals, sensitive sensor interfaces, high accuracy instrumentation devices and many more.

Auto-zeroing
A fundamental auto-zeroing amplifier is provided in fig. 3.1, the proposed amplifier operates in the following manner, when the input clock C1 is on (C2 is off), both of the Vn and Vp are shorted, the feedback loop is closed and the offset that appears at the output is fed back into the input, thus the capacitor (C0 -5 nF) is charged to the offset voltage value, on the other cycle when C2 is on (C1 is off), the amplifier works as usual, meaning that the inputs are fed, at the same time the capacitor charge compensates the offset voltage because they are opposite in sign, this will result in zero offset voltage at the input.  The output signal of the auto-zeroing amplifier (black signal) along with the differential inputs are provided in fig. 3.4, it can be observed that the signal is a sampled version of the amplified inputs, therefore it is not continuous but that is not an issue for this architecture, since it is not used for continuous-time applications. The visible spikes in the output signal can be eliminated using a low-pass filter (LPF).    From the PSS noise analysis in fig. 3.8, it is possible to see how the noise is reduced from 28.696 uV/√(Hz) to 7.821 uV/√(Hz) and the thermal noise is 179.712 nV/√(Hz), the noise reduction is not that powerful in the given architecture, therefore other schemes for auto-zeroing are realized.

Auto-zeroing with an auxiliary amplifier
Another topology exists for auto-zeroing that includes a supplementary (auxiliary) amplifier in its feedback path, this not only significantly reduces the flicker noise, but it also reduces the amplifier's sensitivity to charge injection. Its diagram is shown in fig. 3.9, when the C1 clock pulse is high,  looks quite similar to the output signal of the first auto-zeroing scheme but the difference in that case is, the compensation takes place almost immediately, that is because the capacitor here ( fig.   3.11) charges much quicker than the previous case, despite increasing the circuit's complexity, using a supplementary amplifier is superior to using only one amplifier due to its better performance.  Habitually, the PSS noise analysis is done to see the noise level before and after compensation, the result is presented in fig. 3.12, the noise is reduced from 37.506 uV/√(Hz) to 4.940 uV/√(Hz), that is 158% better than the first AZ amplifier.

Continuous-time auto-zeroing
The previous two auto-zeroing amplifiers were meant to be used in non-continuous applications, they are good in certain applications but should not be used when continuous-time signals are needed, as in voice amplifiers or analog-to-digital converters. A configuration exists that is commonly known as continuous-time auto-zeroing amplifier (CTAZ or ping-pong amplifier), it is a broad term that can be used for any amplifier that implements two identical sub-amplifiers with opposite clock pulses to achieve a continuous signal at the output. A realization of such amplifier is given in fig.   3.13. It's working principle can be summarized in two stages, the first stage when C2 is high (C1 is low), the upper amplifier receives the signal from the differential inputs, amplifies it and feeds it to the output (Vout), at this stage, the lower amplifier's inputs are shorted and it's in compensation mode, in the next stage, when C2 turns into low (C1 is high), the lower amplifier amplifies the signal while the upper amplifier compensates for offset and the output voltage is taken from the lower amplifier, this results in a continuous signal at all times at the output.

Fig. 3.13. Continuous-time auto-zeroing amplifier
The differential inputs and the output signal of the CTAZ amplifier in fig. 3.13 are presented in fig.   3.14, the black signal refers to the output, it is a continuous signal with a DC component of 500 mV, this shows that the offset of 10 mV at the input is removed, a proof that the amplifier is working flawlessly. The visible voltage spikes that can be easily resolved with a low-pass filter. The beginning of the output signal is distorted since the amplifier takes some time to start compensating.  To remove the voltage spikes and other random high frequency components that are caused by switching operations, a Butterworth LPF is connected to the output of the CTAZ amplifier as illustrated in fig. 3.16, the filter's order is 7 with an input and output impedances equal to the CTAZ's feedback resistor value (100 kΩ). The corner frequency is equal to 8 kHz because the clock frequency is 20 kHz and the input signal is 1 kHz, the corner frequency should be higher than the input signal and less than the clock signal, so 8 kHz is a suitable value, picking a different value in the range of 2 kHz to 10 kHz does not result in a major difference.

Chopping
In contrast to auto-zeroing, chopping amplifier does not need any capacitor, it compensates offset voltage using modulation rather than charge compensation, a basic chopper amplifier is presented in fig. 3.19. It consists of two choppers, a fully differential operational amplifier, and a Butterworth low-pass filter. An offset of 10 mV is added as a DC voltage source. The chopper is driven by two clock frequencies of 20 kHz (C1 and C2 are out of phase by 180 degrees) they alternate between 1 V and -1 V as in fig. 3.21, as a rule, the clock frequency should be much higher than the frequency of the input signal. During one cycle "in1" is connected to "out1" and "in2" is connected to "out2", during the other cycle, "in1" will be connected to "out2" and "in2" will be connected to "out1". compensation is given in fig. 3.23, to turn off compensation, the C1 and C2 clocks may simply be replaced with a DC voltage source of 1 V and 0 V respectively, the effect of offset voltage (10 mV) is visible, the differential outputs' DC component is not 500 mV as supposed to be, the signals are displaced, the peak difference is now 10.6 mV (that is nearly equal to the imposed input offset voltage).   The DFT samples taken illustrated in fig. 3.27 further validates the point, output signal's power at 0 Hz is reduced from -37.29 dB to -45.23 dB.

A combination of chopping and auto-zeroing
A combination of both chopping and auto-zeroing can be used to achieve better noise performance, that is a more sophisticated configuration despite its complexity because auto-zeroing part gets rid of the voltage ripples caused by chopping, while chopping gets rid of the noise folding problem that is caused by auto-zeroing. An example of such system is provided in fig. 3.28. The circuit consists of two choppers, placed in the input and the output, and two auto-zeroing amplifiers (upper and lower) are used to achieve a continuous-time signal at the second chopper's input, its operation can be explained simply by the two-phase nonoverlapping clock signals (C1 and C2). When C1 is one and C2 is zero, the upper auto-zeroing amplifier works in amplification mode while the lower auto-zeroing amplifier compensates the input offset of 10 mV, the feedback loop op-amp senses the voltage difference at the output of the main amplifier then the capacitors are charged to this value, later they are amplified and subtracted from main amplifier's output. In the next clock period (when C1 is zero and C2 is one), the system works in a similar manner, but this time the lower amplifier operates in amplification mode and the upper amplifier compensates the offset. This results in a continuous signal as provided in fig. 3.29, though visually it looks like a discrete signal due to sampling and modulation. The voltage spikes and intermodulation products that are visible in fig. 3.29 can be taken out easily with a low-pass filter. The LPF's output is provided in fig. 3.30, it is a signal with removed offset voltage (the signal's DC component is 500 mV, that is the desired value, equal to the commonmode voltage). The circuit takes around of 765.1 us to initiate compensation of offset voltage. Additionally, the used low-pass filter adds to that existing delay, as depicted in fig. 3.31, there is a time delay of 285.7 us, that is equivalent to a phase difference of 102.87 degrees between the filtered signal (black) and the unfiltered signal (red).  Interestingly, the flicker noise reduction rate for an amplifier using both auto-zeroing & chopping is less than the CTAZ amplifier, that is because implementing an amplifier with a combination of both auto-zeroing and chopping needs at least four times more transistors, and that naturally leads to an increase in the flicker noise.

Offset voltage reduction performance
In this section, the previously proposed operational amplifiers with dynamic offset voltage cancellation techniques are compared in terms of their offset voltage reduction performance (i.e., to what extent the offset voltage is reduced). The analysis can be done by measuring the output signal's maximum and minimum values, then their average value is taken which corresponds to the offset voltage level after compensation. Fig. 3.33 illustrates the auto-zeroing amplifier's output signal, the average of the peaks is equal to 500.041 mV, since the input signal's offset value (DC component) was 500 mV and the added offset was 10 mV, a difference of 0.041 mV exists, because the amplifier is unable to reduce it beyond that value (ideally to zero). In short, an offset voltage of 10 mV at the input was reduced to 0.041 mV at the output.

Input-referred voltage noise power spectral density comparison
All the PSS noise analyses done previously in sections (3.1 to 3.5) were done to measure outputreferred noise power spectral density, but in order to have a more thorough understanding of the amplifiers' actual noise performance, input-referred noise PSD must be considered, as in data sheets. Input-referred noise PSD values are achieved by simply dividing the output-referred noise PSD results by the gain (obtained from the amplifier's magnitude response). In this work, the single-ended amplifier has a gain of 69.78 dB, and the fully-differential amplifier has a gain of 47 dB, this converts to voltage gains equal to 3054.9 and 223.8, respectively. Fig. 3.38 provides the inputreferred noise PSD measurement for the auto-zeroing amplifier in section 3.1, the flicker noise is reduced from 9.29 nV/√(Hz) to 2.53 nV/√(Hz), the flicker noise value is quite low, and it is comparable to commercial state of the art operational amplifiers. Fig. 3.38. PSS input-referred noise PSD comparison for the basic auto-zeroing amplifier with (red signal) and without compensation (blue signal) It is worth to mention that the ratio between the flicker noises before and after compensation is equal for input-referred noise PSD and output-referred PSD. The input-referred noise PSD for the op-amp (auto-zeroing with supplementary amplifier) in section 3.2 is given in fig. 3.39, the flicker noise is brought down from 12.153 nV/√(Hz) to 1.616 nV/√(Hz).  pV/√(Hz) with no compensation, this is lowered to 54.87 pV/√(Hz). In comparison with the previously mentioned four configurations, this comes in second place, because the flicker noise after compensation is still more than the flicker noise of the continuous-time auto-zeroing amplifier, nevertheless, that still makes this circuit useful due to its high bandwidth, low voltage ripples at the output and immunity to noise-folding problem.

Thermal performance
Like all electronic circuits, the biasing circuit used in this work is affected by changes in temperature, fig. 3.43 depicts biasing current as a function of temperature. The biasing circuit can operate normally in the temperature range of -40 °C to 85 °C. The biasing current increases with an increase in temperature, higher temperatures lead to a decrease in the transistor threshold voltage and reduction in carrier mobility, this effect increases the drain current. Fig. 3.43. Bias current versus temperature Similarly, the bias voltage is also not immune to variations in temperature, fig. 3  The input-referred noise PSD cannot be measured directly, it can be determined from the outputreferred noise PSD, using the following formula: whereare the average power spectral density of noise voltage of the input and output respectively, V 2 /(Hz); is the voltage gain of the op-amp, it is provided in table 3.3: The thermal performance was considered in section 3.8, the op-amps function properly in the temperature range of -40 °C to 85 °C.
The power supply rejection ratio and the common-mode rejection ratio are provided in table 3.4, PSRR and CMRR can be obtained from these formulas: whereis the common-mode voltage; is the offset voltage and is the drain supply voltage.

Conclusion
In this work, a comparative analysis of CMOS operational amplifiers with dynamic offset cancellation was done. The results of this analysis showed that the dynamic offset cancellation techniques are an effective way to reduce the input offset voltage and its consequences such as flicker noise in operational amplifiers.
Two operational amplifiers were designed (single-output and fully-differential) in 50 nm CMOS continuous-time auto-zeroing must be used, while for amplifying a trigger signal from a sensor, a basic auto-zeroing amplifier can be used despite its humble qualities when compared to other more sophisticated amplifiers.