Enhanced Q-Axis Voltage-Integral Damping Control for Fast PLL-Synchronized Inverters in Weak Grids

The phase-locked loop (PLL) is a commonly used synchronization control method for grid-tied inverters. The PLL-synchronized inverters tend to have poor stability robustness with weak grid interconnections, especially when the PLL is designed with a high control bandwidth. To tackle this challenge, this article proposes an enhanced q-axis voltage-integral damping control, which not only stabilizes PLL-synchronized inverters in weak grids but also lifts the restriction on PLL bandwidth. This superior feature enables inverters to operate stably in ultraweak grids and with a superior transient response. The experimental tests confirm the performance of the method with 400-Hz PLL bandwidth under a short-circuit ratio of 1.28 of the grids.

Abstract-The phase-locked loop (PLL) is a commonly used synchronization control method for grid-tied inverters.The PLLsynchronized inverters tend to have poor stability robustness with weak grid interconnections, especially when the PLL is designed with a high control bandwidth.To tackle this challenge, this article proposes an enhanced q-axis voltage-integral damping control, which not only stabilizes PLL-synchronized inverters in weak grids but also lifts the restriction on PLL bandwidth.This superior feature enables inverters to operate stably in ultraweak grids and with a superior transient response.The experimental tests confirm the performance of the method with 400-Hz PLL bandwidth under a short-circuit ratio of 1.28 of the grids.

I. INTRODUCTION
G RID-TIED inverters are commonly found in renewable power generation systems.A fundamental requirement for operating inverters is the synchronization with the grid, which can be attained in two fundamental ways, i.e., the voltageand power-based synchronization controls [1].The former approach commonly employs a phase-locked loop (PLL), while the latter relies on power control [2].
The synchronization stability of PLL-based inverters has been extensively discussed in recent years [3], [4], [5], [6].Instability is influenced by multiple factors, including both inverter-side and grid-side factors.On the inverter side, high PLL bandwidth [4] and reduced current control (CC) loop bandwidth [5] introduce negative damping to the system, thereby reducing the stability margin.On the grid side, the voltage stiffness at the point of common coupling (PCC) is critical, as the PLL is used to track the frequency and phase of the PCC voltage.Consequently, in weak grids with low short-circuit ratio (SCR), inverters synchronized by PLL exhibit poor stability robustness due to the lack of voltage stiffness [6].
The control scheme that is based on the q-axis PCC voltage, among other alternatives, is commonly adopted [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32], [33].This is due to the fact that the PLL dynamics mostly depend on the q-axis voltage component [26].However, the damping effect of this control scheme can be significantly compromised if the difference between the d-q frame of the physical system and the control d-q frame dictated by the PLL is not considered [29].It is recently revealed in [29], [30], and [31] that this distinction essentially introduces a high-pass filter (HPF) in the q-axis, which, when overlooked, can restrict the allowed bandwidth of PLL.This limitation falls significantly short of the theoretical expectation derived in [26].Such HPF effect is addressed in [29], [30], and [31] by involving an integral (I) action in the controller.However, the integrator is not suitable for practical applications since it can quickly become saturated when there are changes in the q-axis voltage, particularly in the presence of grid frequency deviations [29], [32].This can change the steady-state operation of the system and may even lead to system collapse [32].To address this issue, the integrator needs to be designed as a low-pass filter (LPF) [29], or an auxiliary PLL should be added [32].Yet, these compromises, in turn, nullify the damping effect of the q-axis voltage control [31].
Recently, the I control has been successfully adopted in the qaxis without extra measures in [33].However, the control scheme in [33] is based on a hybrid synchronization control that relies on both the q-axis voltage and active power.Furthermore, the controller design in [33] is based on the active resistance control, and its impact on the bandwidth of PLL-synchronized inverters remains unclear.
In this article, an enhanced active damping method, namely the q-axis voltage-integral damping (Q-VID) control is proposed, whose input is the q-axis PCC voltage, and its output modifies the q-axis current reference.Differing from [33], the approach is implemented with the PLL-synchronized CC, and a codesign method for the Q-VID and PLL is developed, which enables to lift the PLL bandwidth 50 times higher than that recommended in [34], even in ultraweak grids with the SCR below 1.5.Furthermore, unlike [29], [30], [31], and [32], a positive damping effect is ensured by the method in the low-frequency range, even when the frequency approaches zero, eliminating the need of using LPF or auxiliary PLL.Additionally, the parameter design does not require information on grid impedance or operating points, which makes it easy to implement.Finally, the time-domain simulations and experimental results confirm the performance of the method.

A. System Description
Fig. 1 gives the overall circuit and block diagram of vector CC.It contains PLL and CC, as well as alternative voltage control (AVC) to give voltage support.The active power is controlled by setting the d-axis current reference.Boldface notation is used to represent complex space vectors.The superscript s indicates a variable in the α-β frame.If a variable lacks a superscript, it signifies the same variable in the d-q frame, which is defined by the angle θ 1 .The rate of change of θ 1 with respect to time, dθ 1 /dt = ω 1 , represents the regular synchronous frequency.The space vectors v, i, and E correspond to the converter output voltage, phase current, and PCC voltage, respectively.It is  assumed that there is a pure inductive filter on the converter side with an inductance value of L. The grid strength is characterized by SCR, which is the inverse p.u. value of L g .

B. Enhanced CC by Proposed Q-VID Control
Fig. 2(a) shows the detailed configuration of the inner CC in [34].For the AVC, pure I control is employed.The AVC plays the role of voltage support by generating the q-axis current reference.The active power is controlled by setting the d-axis current reference [33].For the CC, a proportional-integral (PI) controller is adopted.According to Harnefors et al. [35], nearperfect steady-state reference tracking can be obtained with a dq coupler and PCC voltage feedforward, even if a P controller is used in CC.Therefore, the I gain of CC is given a very small value only to fix the small error that may occur due to the mismatch of the filter inductance between the actual and model values.This configuration exhibits a narrow stability margin and poor transient performance in weak grids [33].
Fig. 2(b) gives an improved CC configuration by introducing symmetric virtual admittance (VA) [33].The design VA is inherent in the voltage control part of power synchronous control (PSC).Compared with the configuration in Fig. 2(a), this improved structure can ensure stability regardless of the grid strength.However, the transient performance is still not satisfactory due to the low PLL bandwidth.Fig. 2(c) gives the configuration of the inner CC in this article.Due to the thorough analysis and validation of VA analytic design and its effectiveness in [33], this article does not place a primary focus on the impact of VA.Its design is directly inherited from [33].As classified in [4], the frequency range of instability caused by the PLL typically lies around the synchronous (fundamental) frequency f 1 , which generally does not exceed 2f 1 .Therefore, the controller time delay, which impacts the high-frequency behavior of the system, will not be considered.

A. Analysis of Instability Mechanism
The computation of the converter d-q frame angle is performed by the PLL as follows: The symbol s shall be interpreted as the operator d/dt where applicable.Under the steady-state conditions, the converter d-q frame and the grid d-q frame are perfectly aligned.However, when a disturbance occurs at the PCC, it results in an angular error between these two frames.To account for this, the following substitution is made: After linearization, the small-signal model of the PLL is given as where E 0 is the static value of E. As mentioned before, F p (s) is a PI controller.During the normal operation, the grid frequency remains close to 1.0 p.u. with small and slow deviations.Under these circumstances, the I component of the PLL can be rendered very small, and the P component dominates in the transfer function F p (s).Consequently, the PLL can be approximated as a first-order system.In accordance with [34], the P-gain in F p (s) can be determined as α p /E 0 , where α p denotes the chosen PLL bandwidth.In the sequel, the PLL bandwidth, rather than the values of the P and I components, will be used to characterize the PLL.The corresponding small signal of PLL is given in Fig. 3, where ΔE qs and ΔE qc are used to differentiate the q-axis voltage in the grid d-q frame and controller d-q frame.Then, (3) can be put in transfer-function form as The expression of CC is given as where the reference for the converter output voltage v is represented as v ref .
Similarly, the reference for the converter-side current i is represented as i ref .Take Fig. 2(b) as an example, the current reference is generated by both VA and AVC.The design of VA and AVC in this article adheres to the guidelines provided in [34].The gain of AVC is denoted as K v .The inductance of the converter-side inductive filter is denoted as L. F c (s) is a proportional controller with a gain denoted as R a , while H(s) represents the feedforward LPF.The selections for these variables are as follows: where α c is the desired bandwidth of the CC loop.Concerning the LPF bandwidth, letting α f = α c is a useful recommendation [33].In the steady state, the PCC voltage is regulated to E 0 , and with power-invariant space-vector scaling, the active power reference P ref can be accurately tracked by simply letting Similar to (2), after considering the PLL dynamics, the following substitutions are made: where v 0 and i 0 are the static values of v and i.The relation between v and E is described as where steady-state evaluation yields Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.Based on ( 5), (9), and (10), the relation between the current reference and current can be expressed as where 1-H(s) is an HPF, nullifying the low-frequency impact.When H(s) is designed according to (6), the contribution of PCC voltage in the low-frequency range can be considered of less importance [31].Taking the PLL dynamic (8) into consideration, (11) can be simplified as Taking the grid impedance L g into consideration, the relation between the q-axis voltage perturbation and current can be given as Combining ( 12) and ( 13), the block diagram is given in Fig. 4. Fig. 4 shows the block diagram from the current reference to the PLL output.There are three feedback loops in this diagram.Feedback 2 functions as PLL and helps the output converge to 0. Feedback 1 and 3 are the parasitic effects of the PLL.In the steady state, consider a small positive step in the current reference (either d-axis or q-axis; here, the d-axis reference change is taken as an example), the corresponding responses in the q-axis voltage are denoted as Δe qd , which is also positive according to ( 12) The output terms of feedback 1, feedback 2, and feedback 3 are denoted as Δi qpll , ΔE qpll , and Δi dpll .Relations between the feedback terms and the perturbations are given as In the inverter mode, i d0 is positive and i q0 is negative, which means both Δi qpll and Δi dpll are positive.Consequently, feedback 1 and feedback 3 are positive.When there is a small perturbation in the reference, these two branches are trying to drive the output to infinity.

B. Reduction of Equivalent Grid Impedance With Active Damping Control
Feedback 1 and feedback 3 correspond to the PLL impact on the q-axis and d-axis, respectively.Generally, d-q coupling is considered of less importance, especially with low-reactive power exchange [17], [18].Feedback 3 is temporarily omitted here to simplify the analysis.Its impact is considered in Section IV.The current reference change is taken as a disturbance, and Fig. 4 can be simplified as Fig. 5, of which the open-loop gain T is given as The gain demonstrates the interdependence of various factors, including active power (which is generally proportional to the d-axis current), PLL bandwidth, and grid impedance.From Fig. 5, it can be observed that this positive feedback is q-to-q.One straightforward approach to reduce the gain of this positive q-q feedback is to introduce a control from the q-axis voltage to the q-axis current, which is denoted by D(s) in the sequel.Fig. 6 illustrates the basic configuration of the q-axis control, where the q-axis PCC voltage is used to contribute to the q-axis current reference generation, which is denoted as Δi qad here.The system diagram after adding the proposed control is given in Fig. 7.
Take the sum of feedback 1 and the proposed control as the actual feedback term of d 1 .The open-loop gain from input Δd to feedback term d 1 in Fig. 7 is given as where T 1 is the closed-loop transfer function of PLL.By letting D(s) be proportional to Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.where G k is a dimensionless proportional gain.Substituting (19) into (18), the open-loop gain can be rearranged as The D(s) has clear physical insight.If G k is greater than 0, the equivalent grid impedance seen from the q-axis is changed from L g to L g (1− G k ), resulting in better q-axis voltage stiffness.Fig. 8 illustrates two numerical comparisons before and after implementing the damping control, where a small disturbance is added by increasing the active power from 0.9 to 0.95 p.u.The key parameter differences are listed in Table I (case 3 will be illustrated later in Fig. 10), and the detailed parameters can be found in Section V.With the implementation of the damping control, the q-axis voltage response is effectively damped.

C. Interaction Between Q-Axis HPF and Q-Axis Damping Control
Before the implementation of the q-axis damping control, the current reference value is generated through VA, AVC, and current feedforward, and can be represented as follows: (21) The input admittance model of the inverter in matrix form can be expressed as As mentioned in [36], the dynamic system represented in complex-vector form can be transformed into matrix form.By substituting ( 2), ( 4), ( 8)- (10), and ( 21) into ( 5) and rearranging the resulting equation into the format of ( 22), each element of the input admittance matrix can be obtained as follows: After the incorporation of the active damping control on the q-axis, considering the relationship between the current reference and the current, an additional term R a D(s)/(sL+R a ) needs to be included in Y qq in (23).The grid impedance Z g can also be modeled in matrix form According to Skogestad and Postlethwaite [37], the roots of the determinant of I+Z g Y are equivalent to the poles of the closed-loop system.The system is unstable when there are righthalf-plane poles.In the sequel, the root locus of the determinant of I+Z g Y will be used to evaluate the system stability and the effect of the proposed control.
In practical applications, obtaining the actual q-axis voltage in the grid d-q frame is not possible.Only the q-axis voltage from the controller d-q frame is obtainable.In some previous works [20], [21], [22], [23], [24], this difference was ignored for simplicity.However, it should be noted that this simplification can seriously nullify the damping effect of the q-axis damping control, as we will see in the following.
According to (8), the relation between these two voltages can be expressed as Substituting ( 4) into (25), we get Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.It can be seen that the PLL dynamics effectively introduces an HPF in the q-axis of the controller.Although this HPF filter has been identified in some previous works [29], [30], [31], the physical impact of this HPF on the q-axis voltage stiffness has not been discussed in detail.
If the D(s) is still designed according to (19), the equivalent impedance considering the HPF effect is L ge becomes PLL bandwidth dependent.Fig. 9 illustrates how the equivalent impedance changes with increasing PLL bandwidth.It is observed that a higher bandwidth significantly hinders the q-axis damping control from reducing the equivalent grid impedance in the desired low-frequency range.After applying the control proposed in (19), the newly added term in Y qq should be corrected from R a D(s)/(sL+R a ) to In order to further demonstrate the nullification of the active damping effect in the low-frequency range due to the HPF, Fig. 10 illustrates the root locus of Case 3 as G k is gradually increased with a fast PLL.In contrast to the slow PLL cases (case 1 and case 2), the system is still unstable even if the proportional gain is increased to an extremely large value.

D. Modification of the Damping Control Considering HPF Effect
Concerning the fact that only the q-axis voltage from the controller d-q frame can be obtained, the diagram in Fig. 7 needs to be modified, as shown in Fig. 11.The open-loop gain  T should be rewritten as Then, the expression of D(s) considering the HPF effect is immediately given as Taking the HPF filter effect into consideration, the proposed control has an integrator-based format.The system pole plot in Fig. 12 shows G k varying from 0 to 1 (corresponding L ge is from 0.9 p.u. to 0) when SCR is 1.1, and the PLL bandwidth is 8.0 p.u.It can be observed that as G k increases, the system transitions from instability to stability, and the dominant pole moves farther away from the imaginary axis in the left half plane, indicating a greater stability margin.

A. Practical Implementation and Design Guideline
In addition to the HPF effect, the q-axis integrator itself also poses many problems in practical applications.When designing the proposed control, the grid frequency is considered constant.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.However, the actual grid frequency will fluctuate around the rated frequency, and a small integrator gain in PLL at this point will cause the q-axis voltage to converge slowly to 0. In more extreme cases, if a first-order PLL is used, the voltage of the q-axis may not be equal to 0 when the system re-enters a steady state.In this case, the proposed voltage-integral control in the q-axis will quickly saturate and fail, affecting the normal operation of the system.To address this issue, an integrator merging technique similar to [33] is used here by merging all the integrators that contribute to the generation of the q-axis current reference together, as shown in Fig. 13.As seen in (30), the proposed control still has three parameters that need to be adjusted, which is not convenient in practical applications.Therefore, a robust and practical design will be presented based on the previous analysis.
The first step is to remove the dependence on PLL bandwidth α p .Let the α a replace α p in (30), and the value of α a can be set as where α p_max is the upper limit of the desired PLL bandwidth during the practical operation.When the other controllers of the system (AVC, CC, and VA) are designed according to Harnefors et al. [33], with α a designed in this way, the PLL bandwidth can be set arbitrarily if it is smaller than α a .The second step is to eliminate the requirement of the d-axis current information.To overcome this, the base value of the current I b (1.0 p.u.) can be used to replace i d0 and set G k to 1, thus making the design independent of the operating point.The final design guideline of the proposed control is Fig. 14 illustrates the root locus of the system as the PLL bandwidth increases, using the proposed parameterization in (32).The system exhibits excellent stability and robustness even with an ultrafast PLL.

B. Discussion on the Impact of Other Controllers
Fig. 15(a) provides the statistical results of the relationship between the desired CC loop bandwidth and the achievable maximum PLL bandwidth when designed with different gains of the proposed control.The " * " in the figure represents actual statistical data, and the curve depicts a fitted curve derived from the statistical data.Apart from changes in the PLL bandwidth Fig. 14.Root locus of the system when increasing PLL bandwidth with the proposed controller design in (28), with SCR = 1.1.and CC bandwidth, the parameters of all other controllers and the system, including VA and AVC, are consistent with the design of Case1.It can be observed that increasing the CC bandwidth is beneficial for the system's robustness, regardless of whether the proposed control is employed or not.Unless the current loop bandwidth is quite low (e.g., 6.0 p.u.), only then the achievable maximum PLL of the system is significantly reduced.
In this article, I-based voltage control is adopted, and its gain is denoted as K v .As analytical gain design has been extensively discussed in [33], this article directly employs the recommended design.According to Zhang et al. [38], when SCR = 1.1, the desired CC bandwidth is set to 8.0 p.u., and the bandwidth of the ac voltage control loop (AVL) is 1.4 p.u. Fig. 15(b) illustrates the relationship between AVL bandwidth and the PLL bandwidth.The vertical axis represents the maximum PLL bandwidth of the system, while the horizontal axis represents the AVL bandwidth, ranging from 0.28 to 4.2 p.u.It can be observed that, as the AVL bandwidth increases, the maximum PLL bandwidth that the system will tolerate decreases.However, the proposed control still significantly enhances the bandwidth ceiling.When the AVL bandwidth is 4.2 p.u., the maximum achievable PLL bandwidth for the system without the proposed control is 0.05 p.u. Yet, when the gain of the proposed control is set to 10 p.u., the system is still stable when the PLL bandwidth is 4.6 p.u. Fig. 16 discusses the relationship between the PI-type AVC and the PLL bandwidth.When employing a PI-based AVC and still aiming to maintain I domination within the nearsynchronous frequency range, according to Wang et al. [39], the P-gain should be set no larger than one-tenth of K v /2ω 1 .For example, in the numerical example, as provided in Fig. 15(b), Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.K v is set to 1.5 p.u. and the P-gain should not exceed 0.075 p.u. to maintain the I-domination.Such a P-gain design does not impact the PLL bandwidth.Conversely, the scenario involving excessive P-gain is also examined in Fig. 16.It is evident that excessive P-gain can adversely affect the system's stability.However, the inclusion of the proposed damping control significantly enhances the maximum achievable bandwidth of the PLL system.

C. Discussion on Grid Strength and Reduction of Equivalent Impedance
When the proposed control strategy with the positive feedback 1 is integrated, it can be observed that the gain of the proposed control and the grid impedance can be amalgamated into an "equivalent impedance."The proposed design can help reduce the "equivalent impedance."This reduction facilitates the suppression of the attempt by the positive feedback 1 to drive system divergence when the q-axis voltage is perturbed, thus enhancing the stiffness of the q-axis voltage, regardless of whether the inverter is connected to a strong or weak grid.Hence, the proposed control does not compromise the inherent excellent characteristics of a PLL-synchronized inverter under strong grid conditions.With the recommended design value in (32), it can be ensured that in the worst-case scenario (SCR = 1.1, with desired PLL bandwidth, and 1.0 p.u. active power output), the corresponding L ge is reduced to 0. From the perspective of the block diagram, as shown in Fig. 4, the effect of the positive feedback 1 is completely nullified.However, it should be noted that the inherent active power transmission limitations in the actual physical system remain unchanged.

V. SIMULATION RESULTS
Simulations in a weak grid condition are conducted in a p.u. system to verify the theoretical analysis, where the desired CC bandwidth, active power, the amplitude of PCC voltage reference, the filter inductance L, grid impedance L g , and α f are set as 8.0 p.u., 0.9 p.u., 1.0 p.u., 0.08 p.u., 0.9 p.u., and 4 p.u., respectively.Fig. 17 shows the simulated waveform of the system undergoing a PLL bandwidth step before and after adding the proposed control.Fig. 17(a) shows the result before adding the proposed control, which is the same configuration as Fig. 2(b).When α p is changed from 0.2 to 2.0 p.u., the system collapses.Fig. 17     shows the result when the proposed control is added, which is the same configuration as Fig. 2(c).When α p is changed from 0.2 to 2 p.u., the system is still stable.Fig. 18 shows the transient performance comparison.In Fig. 18(a), the system is poorly damped, and the transient performance is unsatisfactory when the PLL bandwidth is only 0.5 p.u. Fig. 18(b) shows the

VI. EXPERIMENTAL RESULTS
Experiments are conducted in both strong and weak grids, with SCR set at 9.7 and 1.28, respectively.The experimental platform is shown in Fig. 19, and the system and controller parameters are listed in Table II.Comparisons of the system without and with the proposed control are shown in Figs.20-23.The system configuration without the proposed control is given in Fig. 2(b).The system configuration with the proposed control is given in Fig. 2(c).Small-signal experimental waveforms in a stiff grid are shown in Fig. 20.In Fig. 20(a), the system becomes unstable when increasing the PLL bandwidth from 7.5 to 8.0 p.u., which is an unusual parameter in practical design, showing that the stability margin is sufficient in a strong grid.In Fig. 20(b), the proposed control is adopted with a gain of 1.0 p.u, and the system is still stable when the PLL bandwidth reaches 8.5 p.u. Transient performance without and with the proposed control is shown in Fig. 21, which shows that the introduction of the proposed control has no adverse effect in a strong grid.
Weak grid experimental results are shown in Figs.22 and 23.In Fig. 22(a), without the proposed control, the system is unstable when the PLL bandwidth is 0.5 p.u.With α a set as 1.0 p.u., the upper limitation of PLL bandwidth is increased to 1.3 p.u., as shown in Fig. 22(b).In Fig. 22(c), when the proposed control gain is set as 10 p.u., the system is still stable when the PLL bandwidth is 1.3 p.u.The above results are consistent with the theoretical analysis in Section III.Additionally, thanks to the merging technique, the q-axis integrator can work well without any compromise or extra PLLs.
In Fig. 23(a), the PLL bandwidth is set to 0.2 p.u., resulting in a stable system but unsatisfactory transient response due to the slow PLL, which causes a noticeable overshot in the q-axis voltage when there is a step change in active power reference.In Fig. 23(b), the PLL bandwidth is increased to 1.0 p.u., leading to an improved transient response but significantly reduced stability margin.The system becomes unstable when the active power reference is set from 0.5 to 1.0 p.u.In Fig. 23(c), setting α a to 1.0 p.u. effectively enhances the stability margin and transient response.In Fig. 23(d), when the proposed control gain is set to 10 p.u., the system is still stable when the PLL bandwidth is set to 8.0 p.u., which is the PLL bandwidth upper limit in a stiff grid, as demonstrated in Fig. 20(a).Fig. 23(d) demonstrates that the proposed control solution provides both excellent transient performance and stability robustness, regardless of the grid impedance and power rating.

VII. CONCLUSION
In this article, a Q-VID control that is independent of the information on PLL parameters and operation points is proposed.The structure and parametrization are intuitively obtained by block diagram modeling.After the proposed control is added, the q-axis voltage is equivalently stiffened, allowing the PLL to be operated as if it were in a strong grid.Additionally, problems with Q-VID control in applications have been solved, making it straightforward to implement in practice.The high stability robustness of the system with ultrafast PLL even in a very weak grid is enabled by the proposed Q-VID control, as demonstrated by both numerical simulations and experimental results.

Fig. 4 .
Fig. 4. Block diagram from current reference to output angle.

Fig. 6 .
Fig.6.Basic configuration of the q-axis active damping control.

Fig. 10 .
Fig. 10.Root locus of the system when increasing G k from 0 to 70 p.u. of Case 3.

Fig. 11 .
Fig. 11.Implementation of the proposed control considering the difference between d-q frames.(a) Actual implementation.(b) Equivalent transformation.

Fig. 12 .
Fig.12.Root locus of the system when G k is increased from 0 to 1, with SCR = 1.1 and α p = 8.0 p.u.

Fig. 13 .
Fig. 13.Merging the I-parts of AVC and proposed control.

Fig. 15 .
Fig. 15.Relationship between the maximum achievable PLL bandwidth and different Q-VID control gains in p.u. with respect to (a) CC loop bandwidth and (b) AVL bandwidth.

Fig. 16 .
Fig. 16.Relationship between the maximum achievable PLL bandwidth and different Q-VID control gains with respect to the proportional gain of the AVC. (b)

Fig. 17 .
Fig. 17.Simulation waveforms with α p changing from 0.2 to 2 p.u. when SCR = 1.1.(a) Before adding the proposed control.(b) After adding the proposed control.

Fig. 18 .
Fig. 18.Simulation waveforms of transient performance, when SCR = 1.1.(a) Before adding the proposed control.(b) After adding the proposed control.

Fig. 20 .
Fig. 20.Experimental results of the strong grid with a PLL bandwidth step change.(a) Without the proposed control.(b) With the proposed control.

Fig. 21 .
Fig. 21.Experimental results of the strong grid with a d-axis current reference change.(a) Without the proposed control.(b) With the proposed control.

Fig. 22 .
Fig. 22. Experimental results of the weak grid with a PLL bandwidth step change.(a) Without the proposed control.(b) With the proposed control gain set to 1.0 p.u. (c) With the proposed control gain set to 10.0 p.u.

Fig. 23 .
Fig. 23.Experimental results of the weak grid with a d-axis current reference change.(a) PLL bandwidth is 0.2 p.u. without the proposed control.(b) PLL bandwidth is 1.0 p.u. without the proposed control.(c) PLL bandwidth is 1.0 p.u. with the proposed control.(d) PLL bandwidth is 8.0 p.u. with the proposed control.

TABLE I PARAMETERS
OF DIFFERENT CASES (P.U.)

TABLE II PARAMETERS
OF THE EXPERIMENTAL PLATFORM AND THE CONTROLLERS