Abstract
By its very nature, Spin Wave (SW) interference provides intrinsic
support for Majority logic function evaluation. Due to this and the fact
that the 3-input Majority (MAJ3) gate and the Inverter constitute a
universal Boolean logic gate set, different MAJ3 gate implementations
have been proposed. However, they cannot be directly utilized for the
construction of larger SW logic circuits as they lack a key cascading
mechanism, i.e., fan-out capability. In this paper, we introduce a novel
ladder-shaped SW MAJ3 gate design able to provide a maximum fan-out of 2
(FO2). The proper gate functionality is validated by means of
micromagnetic simulations, which also demonstrate that the amplitude
mismatch between the two outputs is negligible proving that an FO2 is
properly achieved. Additionally, we evaluate the gate area and compare
it with SW state-of-the-art and 15nm CMOS counterparts working under the
same conditions. Our results indicate that the proposed structure
requires 12x less area than the 15 nm CMOS MAJ3 gate and that at the
gate level the fan-out capability results in 16% area savings, when
compared with the state-of-the-art SW majority gate counterparts.