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Fast and Area Efficient Hybrid MTJ-CMOS Spintronic Approximate Adder

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posted on 11.03.2022, 03:41 by Gulafshan GulafshanGulafshan Gulafshan, Dr. Mohd. Hasan, Mohd. Arqam Khan
Present-day scenarios demand high computational power, compact, fast, and less power-hungry components. To resolve these critical issues one attempt is to integrate emerging magnetic devices with existing conventional technologies. The applications in which accuracy can be compromised to some extent in a trade-off for other attributes like energy, area, and delay is approximate computing. An efficient full adder circuit is crucial for arithmetic operations. This paper proposes a novel spintronic approximate full adder circuit based on an emerging magnetic tunnel junction (MTJ) which offers partial non-volatility, low energy consumption, area efficiency, and speed over an exact adder. By performing the simulations, the effect of STT, SHE, and VCMA switching schemes are demonstrated on the performance of the adders. The superiority of the proposed adder circuit at the fixed optimum value of VCMA and Hext over the existing adder is also shown. The proposed design has an exact carry output and approximate sum output with an accuracy of 62.5%.

History

Email Address of Submitting Author

gulafshan.mau@gmail.com

Submitting Author's Institution

ZHCET, Aligarh Muslim University

Submitting Author's Country

India