Fixed-Frequency PWM Control and Stability of Series-Stacked Buffer for 2ω-Power Decoupling

Active second-harmonic ( $2\omega $ ) filters have become an integral technology for single-phase power converters in high-power density designs. The series-stacked buffer (SSB) has emerged as an attractive topology among the existing solutions due to its low power, high efficiency, and compact design. However, one of the challenges in adopting SSB lies in its control, where hysteresis current control has been adopted conventionally. This results in a wide variation in the switching frequency, making the digital control implementation and filter design complex. On the other hand, fixed-frequency pulsewidth modulation (PWM) control necessitates developing a model for the systematic controller design to ensure stability and desired filtering performance. The assumption of SSB modeled as a second-harmonic current source, independent of the dc bus circuit components, fails to capture the dc bus loading effect on the SSB. In this work, a dynamic model of SSB is developed where the main dc bus and its passive elements are considered. The derived model enables a systematic approach for the controller design while ensuring the desired $2\omega $ filtering. The stability limits and parameter sensitivities of the model are studied analytically and in simulations. The analytical model is validated, and the proposed controller performance and stability limit are verified experimentally on a hardware prototype. A video demonstrating the transition from stable to unstable operation is provided.


I. INTRODUCTION
A CTIVE power decoupling (APD) technology has emerged as a replacement for large electrolytic capacitors in single-phase voltage source converters (VSCs) for filtering the second-harmonic current. Single-phase VSCs are widely adopted for grid integration of renewable sources, electric vehicles, traction drives, etc., [1], [2], [3]. The growing concerns over reliability, life expectancy, and power density of the converters have driven the study of many APD topologies [4], [5], [6], [7], [8], [9], [10], [11] in recent times. While the capacitance reduction remains the primary focus in all these proposed embodiments, the additional circuits, control efforts, and efficiency implications of different filter topologies are compared in the literature [10], [12] to select an optimal solution for a given application. In general, the topologies which filter out the second-harmonic current ripple employ an auxiliary switching leg connected across the main dc bus [4], [6], [7]. Thus, the voltage rating of the auxiliary leg becomes equal to the main dc bus voltage, as depicted in Fig. 1(a) for the configuration of [4]. The figure indicates that the filter requires an extra switching leg of the same voltage rating as the main converter but a current rating equal to the second-harmonic current. Contrarily, the series configuration-based APD topology, depicted in Fig. 1(b), uses an auxiliary H-bridge whose voltage rating, decided by the peak of the second-harmonic voltage ripple across C f , can be made small [13]. A drawback of this configuration is that the auxiliary converter needs to carry the dc current along with the second-harmonic current required by the series capacitor C s for ripple cancellation. Thus, the rms current through the auxiliary converter increases. In addition, the presence of substantial second-harmonic ripple across C f increases voltage stress on the main converter.
As the switching and conduction losses in a power converter increase with voltage and current rating, a low-voltage-lowcurrent auxiliary circuit is the most desirable for enhancing the efficiency of the APD topologies. Moreover, low-operating voltage allows higher switching frequency which enables the size-reduction of the passives of the auxiliary converter. Technologies like DirectFET, OptiMOS [14], GaN HEMTs [15], etc., provide high-efficiency, low-voltage devices for highswitching frequency applications. The series-stacked buffer (SSB) [10], shown in Fig. 1(c), is one such configuration that is realized with a low-voltage, low-current auxiliary converter called the buffer converter. Unlike in the series configuration, only the second-harmonic component of the dc-link current flows through the buffer converter, making its rms current lower than that of the series APD topology. The comparison with different existing topologies surveyed in [10] indicates that SSB offers an efficiency (99.4%) closest to that of passive filtering solution and the highest energy density among the other active filtering solutions due to its high switching frequency. Therefore, SSB is considered a promising active filter topology [16], [17], [18], with its task not limited to only second-harmonic ripple filtering. Numerous prospective applications of SSB have motivated research on its optimal design [19], operational aspects [20], and control techniques [10], [21]. A current hysteresis control approach has been adopted for controlling the SSB in [10] and [22], and a voltage-based 2168-6777 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
control scheme is proposed in [21]. However, the model of the buffer converter required for implementing the control strategies under a wide range of operating conditions has not been analyzed in detail. While stability is not a typical concern for hysteresis control and is often a reason for its adoption, average voltage-mode control necessitates the plant model to design a controller that ensures desired performance and stability. Therefore, it is essential to derive a plant model of SSB, incorporating the main converter and its dc bus components. Current-mode control with hysteresis controller is often simpler to implement with no need for a plant model; however, current-mode control for SSB applications has several challenges.
1) Sensing of dc-Link Current: Placement of the current sensor in the dc-link introduces unwanted power-loop inductance in the current commutation path of the main converter [22]. 2) Reference Current Estimation: Analytical estimation of dc-link current eliminates the dc-link sensor but causes inaccuracy due to finite turn-on, turn-off time, and deadtime of the switches [23].
Further, hysteresis control has the following concerns.
1) It causes the switching frequency of the buffer converter to vary over a wide range, resulting in increased switching loss and challenges in EMI filter design [24]. 2) The finite clock frequency effect gives rise to inaccuracies in digital hysteresis implementation [25]. 3) With inaccurate current hysteresis control, dc offset voltage appears across C 3 [10]. Therefore, an additional voltage control loop is required to alleviate the offset, which, otherwise, increases the voltage rating of the buffer converter. 4) Modified hysteresis control in the digital domain adds to the control complexities [26] while analog realization poses concerns over noise susceptibility and signal integrity.
The above concerns make the voltage-based control method preferable, as indicated in [21] and [22]. Though the dc-bus current sensing requirement is eliminated in [22], the buffer converter is still operated in current control mode using a hysteresis controller. On the other hand, Wang et al. [21] implements the voltage control through an open-loop control scheme and does not provide a plant model using which the controller design and stability assessment can be approached analytically. In view of the above, the present work develops the buffer converter model to design its control and study its stability limits. It is realized that despite its similarity with H-bridge single-phase VSC, the unique load characteristics and second-harmonic voltage tracking objective of the buffer converter make its plant model critical for designing a stable control loop. The major contributions of this work are as follows.
(i) An analytical nonlinear dynamic model is developed for the buffer converter of the SSB. (ii) This model is linearized considering a nominal load that incorporates the main and buffer converter parameters. This gives a third-order model for the buffer converter along with the load. (iii) A simplified second-order equivalent model is obtained for the voltage-mode control of the buffer converter, which aids the controller design. (iv) Uniqueness of load impedance characteristics seen by the buffer converter and its sensitivity to circuit parameters are analyzed. (v) A step-by-step design of a voltage-mode controller for the buffer converter is elaborated. The stability limits in terms of controller parameters are provided. (vi) A fixed frequency carrier-based pulsewidth modulation (PWM) is implemented in place of the variable switching frequency hysteresis control. (vii) The model is verified by operating the system in a closed-loop with the designed controller. Congruence of control limits found from the analytical model, simulation, and experimental results validate the analysis. Amongst these, (i)-(iv) focus on the modeling and demonstrate the need for the buffer converter model; (v) and (vi) highlight the contributions that replace the current hysteresis control with the voltage-mode control, with the stability range of the controller parameters identified; and (vii) validates the plant model, controller design, and stability limits.

A. Source of Second-Harmonic Ripple
Second-harmonic ripple is generated due to the mismatch between instantaneous input and output power in single-phase converters [1]. Referring to Fig. 1(c), let the instantaneous expressions for the main converter output voltage and current be given by (1), where, φ is the power factor angle v ac = V m cos χt, i a = I a cos (χt + φ) .
If the voltage ripple in v dc is small enough, it is assumed that v dc = V dc , which is the average value of v dc . Therefore, the switching cycle averaged expression for the dc-link current is where f sm = (1/T sm ) is the switching frequency of the main converter. Equation (2) shows that the switching cycle averaged dc-link current i inv Tsm consists of two components In order to ensure that the second-harmonic (2χ) ripple component i r is not drawn from the dc source, SSB is controlled to inject i r to the dc-link. This is achieved when SSB offers the minimum impedance at 2χ frequency with respect to other parallel branches across the dc-link. Fig. 1(c) shows a single-phase inverter with an SSB-based APD circuit [10]. The SSB unit, consisting of a series combination of main capacitor (C 1 ) and buffer converter, is connected across the main dc bus. The capacitor C f across the dc bus filters out the switching frequency ripple of the main VSC. When the buffer converter of SSB is perfectly controlled, it draws the entire second-harmonic current, i 2 = −i r , from the dc-link current i inv . This causes a secondharmonic voltage drop (v c1,2ω ) across the main capacitor C 1 , on top of its average voltage V dc . As C 1 blocks the dc voltage V dc , the voltage rating of the buffer converter gets reduced.

C. Review of Operation and Control
The buffer converter is operated in either current or voltage control mode. In current control, the buffer converter current i b is controlled such that i b = i 2 . This automatically ensures that at 2χ frequency, the impedance of SSB is minimum compared to the other parallel paths, consisting of C f and R s . In voltage-mode control, the lowest impedance of the SSB branch is ensured by canceling the 2χ voltage drop across C 1 by the voltage across C 3 . Thus, the net second-harmonic voltage always becomes zero across SSB, driving the entire i 2 into it. However, owing to the loss in the SSB circuit, the 2χ voltage drop across the main dc bus is never zero in practice, but a small resistive drop exists in phase with i 2 . At steady state, this voltage drop across the main dc bus drives a small amount of second-harmonic current into the dc source. This current becomes negligible with higher R s . However, a small R s can make the second-harmonic filtering ineffective, as discussed in [27]. An impedance emulation approach to increase the effective source branch impedance is proposed in [28] to mitigate the problem due to small R s . Referring to Fig. 1(c), in current-mode control, i b tracks the negative of the second-harmonic component (−i r ) of the dc-link current i inv . Thus, it requires two current sensors: one for sensing i inv and the other for i b , as implemented in [10]. The conventional hysteresis-based current control causes dc voltage offset across C 3 due to control imprecision [10]. This leads to non-optimum utilization of the capacitor C 3 and increased voltage rating of the buffer converter [10]. Therefore, an additional voltage control loop is incorporated in [10] and [22], that needs sensing of v c3 . In voltage-based control, the voltage across C 3 is controlled to cancel the second-harmonic voltage drop across C 1 . Unlike the current-mode control,  it does not require the two current sensors. Moreover, the voltage controller applies the required zero-average secondharmonic voltage across C 3 without any extra control loop. However, the plant model is an essential prerequisite for the proper design of the voltage-mode controller. As the choice of different passives and parameters impacts the plant dynamics, the design of the passives is briefly discussed in Section III before developing the buffer converter model.

III. DESIGN CONSTRAINTS FOR PASSIVE COMPONENTS
The passive components in the converters are selected to obtain desired filtering performance, achieved through suppression of voltage and current ripple. Table I lists the key design parameters for main and buffer converters. Expressions for switching ripple in the inductor current and capacitor voltage are calculated, assuming unipolar modulation for both. Table II provides the voltage and current ripple expressions relevant for setting the ripple constraints for component selection. It is to be noted that the selected design parameters in Table I are not optimal; however, the maximum ripple criteria are consistent with [10]. For optimal design of SSB with respect to loss and volume, Liao et al. [29] can be referred. It is shown that the modeling and analysis in Section IV are valid both for the present design as well as the optimal design.

A. Main Converter: Current Source Model
For modeling the SSB, the main converter is initially considered a current source that draws a current equal to the dc-link current i inv . The main converter is controlled with an inner current loop for the ac current (i a ) control and an outer voltage loop for the dc bus voltage (v dc ) control [30].  Input impedance Z in (s) characteristics looking into the main converter from its dc terminals, depicting frequency responses for (a) load variation from 20% to 100%, (b) current loop bandwidth variation from 500 Hz to 2 kHz at rated load, and (c) filter inductance Lac variation between 1% and 20% of base impedance Z base .
i a , and v dc be the modulation signal, ac current, and dc voltage of the main converter. For the linearized model, smallsignal perturbationsm m ,ĩ a , andṽ dc are considered on their respective steady-state amplitude, and dc values: M m , I a , and V dc , respectively. The block diagram also depicts the relation between the dc-link current i inv and the ac current i a . G m c (s) is a PR-controller for the current control loop that is faster than the outer dc voltage control loop. The design steps for the main controller follow the method suggested in [30]. The fast current-loop dynamics lead to the assumption of the current source approximation of the main converter while studying the dc voltage dynamics. Looking back from its dc terminal, the closed-loop input impedance Z in (s) of the main converter is calculated from Fig. 2(a) and (b). If Z o (s) is the output impedance of the main converter, taking the filter and load impedance together, the closed-loop input impedance Z in (s) is found as follows: Considering no change in the current reference (ĩ * a = 0) due to slow dc voltage loop dynamics,m m = −G m c (s)ĩ a . Thus, .
The frequency response of the impedance Z in (s), given by (5), is depicted in Fig. 3(a)-(c) for different loading, current loop bandwidth, and choices of filter inductance L ac , respectively, for unity power factor operation. The main converter parameters are as given in Table I. The controller G m c (s) is a PR controller that achieves 1 kHz bandwidth with proportional gain k p = 0.02/A, resonant gain k r = 5/(A·s), and damping ratio ζ m = 0.02. It is seen that for rated load and nominal control loop bandwidth (1 kHz), the closed-loop input impedance Z in (s) is sufficiently large (≥40 dB · Ω) at 2χ frequency (100 Hz). Fig. 3(a)-(c) indicates that Z in (s) increases further with reduced loading, increased bandwidth, and filter inductance L ac . However, in the present design, the choice of filter inductance (2% of Z base ) is driven by the ripple criteria, discussed in Appendix and is consistent with the design in [31] and [32]. Even without a high L ac , a proper current loop design ensures the main converter's current source behavior at the second-harmonic frequency. A high-input impedance validates the current source assumption for different current loop bandwidths and a range of loading.

B. Model of the Buffer Converter
Based on the above analysis, the main converter is considered as a current source while modeling the buffer converter. The switching cycle averaged model of the buffer converter is developed as follows. If the duty of the buffer as depicted in Fig. 4(a). The duty cycle of the buffer converter is related to its modulation m b (t) by d b (t) = 0.5 + 0.5m b (t), considering unipolar modulation. The average model is obtained in Fig. 4(b), representing the voltage output of the buffer converter with d b v b . The main converter is represented as a controlled current source of current i inv due to the reason explained in Section IV-A. The model includes the dc source v s and all the passive components connected to the main dc bus. Applying Kirchhoff's current and voltage laws on the equivalent circuit of Fig. 4(b), the following equations pertaining to the average model are obtained: Equations (6a)-(6d) indicate that the averaged model obtained is non-linear. A linear model is derived by applying the small-signal linearization method to the average model, given by (6a)-(6d). The derivation of the small-signal model from the averaged model of the converter is detailed in [33].   .
where A and B are given by (8) and (9), respectively, In the state-space model,d b is the control input, {ṽ b ,ĩ inv ,ṽ s } are the disturbance inputs, and {ṽ c3 ,ĩ b } are the outputs for voltage-mode control and current-mode control, respectively. The voltage v b across capacitor C 2 is considered as a disturbance input as v b is a stiff voltage with negligible voltage ripple. The capacitance C 2 is designed to ensure this. In addition, the slow control loop dynamics of v b allow it to be considered as a constant while designing the control loop for v c3 . The resultant generalized plant model lends itself to the design of controllers for voltage as well as average current-mode control. Due to the advantages of the voltage-mode control, mentioned in Section I, this control approach is implemented in Section V, whereṽ c3 is considered as the output variable.
In the equivalent circuit of the state-space model in Fig. 4(c), the control and disturbance inputs are marked in blue and red, respectively. The buffer converter, along with the main converter's characteristics, is thus, captured by a third-order model, given by (7)- (10).

C. Reduced-Order Model for Voltage-Mode Control
The equivalent circuit for the voltage-controlled plant model is obtained, equating the disturbance inputs in Fig. 4(c) to zero and shown in Fig. 5(a). It shows that the equivalent load on the buffer converter, represented by Z Load (s), is The equivalent circuit representation of Fig. 5(a) facilitates direct derivation of the plant transfer function for the voltagemode control. Thus, the plant transfer function is found as follows: The coefficients a j : j = 1, 2, 3, b 1 and gain k gv in (12) are expressed in terms of the circuit parameters and provided in Table III. The plant model can be simplified to a second-order model with proposed approximations, given in the Appendix. This provides insight into the system response and the required control structure. Thus, (12) is simplified to G pve (s) in (13) represents a second-order equivalent plant model with resonance frequency χ r = a 1 /a 3 and damping ratio ζ = (1/2)(a 2 / √ a 1 a 3 ). The impact of the changes in the main converter parameters on the buffer converter response is predicted from the resonance frequency χ r and damping ratio ζ of the model in (13). Fig. 5(b) provides an equivalent circuit representation for the reduced-order model of the buffer converter. It is noted that the buffer converter sees an equivalent capacitive load C e , and the effective series resistance of the filter inductor (L b ) gets modified from R Ls to R e , where The equivalent circuit corresponding to the reduced-order plant model facilitates a quick approximation of the resonance frequency, which aids the controller design. Fig. 5(b) indicates that the resonance frequency of the plant G pve (s) is χ r = 1/ √ L b C e . Using (14), and assuming C 1 C f and C f C 3 , sequentially, the limits for χ r is obtained Thus, with the proposed approximation, it is possible to reduce the exact plant model of the buffer converter into a second-order model, which allows an intuitive prediction of its response, characterized by resonance frequency χ r and damping. However, parameter variations can modify the plant model, resulting in degraded closed-loop performances. Therefore, the effects of parameter variations on the plant characteristics are assessed below.

D. Parameter Sensitivity Impact on the Reduced-Order Model
For parameter variations, a (±10%) range is considered for different circuit components. Based on the constraints of model order reduction in Appendix, it is observed that the model simplification remains valid for the considered range of parameter variations. Therefore, the focus is to investigate the effect of these variations on the reduced second-order model, which is used in the proposed design of the controller. In order to evaluate the sensitivity, the equivalent circuit of the second-order plant model G pve (s), shown in Fig. 5(b), is considered. The expressions of equivalent circuit parameters C e and R e , given by (14) and (15), indicate that apart from the buffer circuit parameters, dc bus filter parameters and source resistance also impact buffer converter loading. While the change in C e modifies the resonance frequency of the equivalent plant model, any variation in R e affects the damping. Thus, the closed-loop performance and stability of the buffer converter can get affected. Let the sensitivity of the equivalent circuit parameters C e and R e upon the variations of the physical circuit parameters be defined as

E. Impact of the Effective Load Model on SSB
Despite being similar to a single-phase VSC in configuration and operation, the capacitive nature of its equivalent load makes the buffer converter control challenging. In conventional applications, e.g., solar inverters, or machine drives, VSC is subjected to an inductive, resistive, or no load. As opposed to those applications, the buffer converter in SSB is subjected to a capacitive load, as found in its equivalent model in Section IV-C. In order to explain the specialty of capacitive  loading compared to other loads, different types of loading are considered on the average model of the buffer converter in Fig. 6(a). The transfer function [G p (s)] between the output voltageṽ c3 to dutyd b for different loads are found from the small-signal equivalent model of the circuit in Fig. 6(a) and given by (17a)-(17d). Corresponding frequency responses are depicted in Fig. 6(b), with the parameters marked in the figure. Equations (17a)-(17c) indicate that the resonance frequency of the plant does not depend on the load if: 1) R Ls R L and 2) L b L L , both of which are realistic assumptions. However, for capacitive loading, (17d) indicates that the resonance frequency is a function of the load C L In Fig. 6(b), the frequency response of G p (s) shows that the resonance frequency χ r shifts to a lower value in the case of capacitive load. As χ r decreases, its impact on the bandwidth and stability of the closed-loop system becomes more prevalent. Hence, it is essential to consider a nominal load, given by (14) and (15), in the buffer converter model as it is subjected to equivalent capacitive loading.

V. CONTROL PARAMETERS SELECTION AND STABILITY
In voltage-mode control, the objective of the controller is to generate a voltage across C 3 , which cancels the second-harmonic voltage drop across C 1 . Fig. 7(a) shows the schematic for the voltage-mode control of the buffer converter along with the main converter control loops. The reference v * c3 consists of two components: 1) ripple cancellation component v * c3,r and 2) active power balance component v * c3,a . The ripple cancellation component is synthesized from the voltage across C 1 , the second-harmonic component of which is extracted with a bandpass filter (2χ BPF). Let us assume that the buffer converter draws the entire second-harmonic current i 2 . Therefore, a voltage v * c3,a , in phase with current i 2 is required to be applied across capacitor C 3 to ensure active power flow into the buffer converter. Since i 2 is not sensed in voltagemode control, the phase information of i 2 is derived from the measurement of v c1 , as in [18]. As i 2 = C 1 (dv c1,2ω /dt), the band-limited derivative of v c1,2ω is calculated to obtain the phase information of i 2 . The amplitude of v * c3,a is decided by the output of PI controller G P I (s), which maintains the average voltage across C 2 to the desired voltage level.
The voltage across v c3 is compared against the reference v * c3 , and the error is processed through controller G cv (s).
The output of the controller is compared in the modulator with a triangular carrier to obtain the switching pulses for the buffer converter. Thus, the present control scheme generates the pulsewidth modulated switching signals at a fixed frequency f sa .

A. Discrete-Time Plant Model
The digital realization of the controller requires sensing and analog to digital conversion of the voltages v c1 and v c3 . Fig. 7(b) shows the block diagram representation for the voltage-mode control, taking the sampling and PWM delays into account. An effective delay of 1.5T sp is considered in the voltage control loop while designing the controller [34]. The delay is modeled as E −sT d , where loop delay T d = 1.5T sp and T sp = 0.5/f sa if the sampling is performed twice in a switching cycle. Thus, the reduced-order plant model with the delay is represented as Similarly, the exact third-order plant model with loop delay is represented by G pv (s). Henceforth, the "plant model" will refer to the "plant model with loop delay." Fig. 8(a) shows the magnitude and phase responses of the exact and reducedorder approximated models, which closely match each other.
A rapid fall of phase in the vicinity of the Nyquist frequency is noted due to the phase lag contributed by the loop delay.

B. Validity of Reduced-Order Plant Model
The frequency responses of the exact [G pv (s)] and the reduced-order [G pve (s)] plant models, depicted in Fig. 8(a), are indistinguishable as long as the assumptions stated in (A.7) and (A.9) are true. To verify this, variations in C 1 and R s are considered. C 1 is varied between 10 to 200 μF while R s is varied between 1 Ω to 10.5 Ω. The variations in the plant parameters a 1 , (a 2 /a 1 ) and (a 3 /a 2 1 ) with C 1 and R s are depicted in Fig. 8(b). It shows that in the highlighted region of the plot, where both C 1 and R s are small, (A.7) does not hold. Similarly, Fig. 8(c) indicates that condition (A.9) is not valid for small values of C 1 and R s where the ratio (a 1 /b 1 ) deviates from 1. The effect of small values of C 1 and R s are depicted in the frequency responses of the exact and reduced-order plant model in Fig. 8(d) for two sets of values: C 1 = 200 μF, R s = 1 Ω and C 1 = 20 μF, R s = 1 Ω. It is noted that the frequency responses of the exact and reduced-order plant model are distinguishable from each other for C 1 = 20 μF and R s = 1 Ω. However, the choice of such small capacitance for C 1 is not practical as it increases the amplitude of 2χ ripple across it, thereby increasing voltage stress on the capacitor C 3 and the buffer converter. The resistance R s , being a system parameter, can be as small as 1 Ω; however, that does not cause any significant deviation in the frequency responses as long as the capacitance of C 1 is sufficiently large, as indicated in Fig. 8(d). Thus, it is inferred that practical design values do not cause a violation of model order reduction criteria. For the optimal design parameters [29], the validity of the model order reduction criteria are verified and presented in Appendix.

C. Controller Structure
For accurate reference tracking, the controller G cv (s) is designed by applying internal model principle [30], which places a complex pole at χ 2 = 2χ. However, the complex conjugate pole pair causes a phase jump from 0 • to −180 • just after χ 2 . Hence, a first-order zero is added at χ = χ z to avoid the phase crossover at χ 2 . The location of χ z is chosen at least one decade below χ 2 so that an adequate phase margin is obtained. Thus, the controller transfer function becomes G cv (s) is a resonant controller with resonant gain k r , which decides the gain crossover frequency (GCF) of the loop gain

D. Limit on GCF
From a positive phase margin requirement, the maximum achievable GCF, which is also indicative of the bandwidth of the closed-loop controlled system, can be obtained. A positive phase margin is essential to ensure stability, while practical design requires a higher phase margin to ensure acceptable overshoot in the response and account for delays, nonidealities, changes in parameters, and operating points. For the voltage controller G cv (s), the maximum achievable crossover frequency is evaluated here considering two cases: 1) GCF > χ r and 2) GCF < χ r . If the GCF is χ c , the phase margin for case 1) is As χ c > χ 2 and χ z = χ 2 /10, tan −1 ωc ωz (π/2). Thus, (21) gets simplified to (22) As the right-hand side of (22) is greater than (π/2), for any positive value of φ P M | ωc>ωr , χ c cannot be greater than χ r . This shows that with resonant controller G cv (s), the achievable bandwidth or GCF for the voltage-controlled plant is always less than the resonance frequency χ r . For case 2), when χ c < χ r , the expression for phase margin is For φ P M | ωc<ωr = 50 • , the transcendental equation (23) gives χ c = 2π krad/s . However, owing to the small damping of the plant (ζ = 0.204) gain margin becomes negative, leading to unstable operation. This indicates that even though the phase margin is sufficient for χ c < χ r , selection of k r must ensure a sufficient gain margin for a stable control loop.

E. Limit on k r
Considering the loop delay, the root-locus of the loop gain L v (s) is shown in Fig. 8(e). For k r > k critical , the system poles move to the right half of the s-plane, making the closedloop system unstable. For the converter parameters given in Table I, the value of k critical is found to be 122 and 115 for the reduced-order plant model G pve (s) and the exact plant model G pv (s), respectively, pertaining to the voltage and power levels of the scaled prototype, given in Table V. The frequency responses of the loop gains for both the plant models are compared in Fig. 8(f), considering k r = 10 and 115. With k r = 10, phase margin and gain margins are 80 • and 23 dB, respectively, while the crossover frequency is χ c = 250π rad/s. As k r is increased to 115, despite having a sufficient phase margin of 62 • , only a small gain margin (1 dB) is obtained. In Fig. 8(f), the zoomed views of the magnitude plot at the resonance frequency (χ r ) depict that the gain of the reduced-order model is 0.5 dB less than that of the actual plant model. For lower values of k r , this difference in gain does not translate to any significant difference in the time response as the gain margin is sufficient. However, for higher k r , the resonance oscillation in the voltage v c3 becomes more pronounced than that predicted by the reduced-order model. Therefore, while targeting a bandwidth (χ c ) close to the resonance frequency (χ r ), it is necessary to ensure sufficient gain margin to compensate for this slight deviation in gain between the exact and the reduced-order plant model. In order to verify this, the closed-loop system is given a unity peak sinusoidal test input of 2χ frequency (100 Hz), as depicted in Fig. 8(g), considering the exact and the reduced-order plant model. For k r = 10, when GCF is much less than χ r , both the models exhibit identical settling times and steady-state performances. However, for k r = 115, when GCF is close to χ r , the closed-loop response of the exact plant model shows a higher magnitude of resonance frequency oscillation. Thus, the maximum value of k r is limited to avoid resonance-induced oscillation caused by an inadequate gain margin. Controller parameters and limits are tabulated in Table VI.

VI. VERIFICATION OF MODEL AND CONTROLLER
The plant model is verified by operating the SSB in closedloop control with the designed voltage-mode controller. The fulfillment of desired control objective, agreement of analytical and experimental stability limits of controller parameters and response times are provided for the validation of the model.  The experiments are conducted on a scaled prototype with specifications given in Table V. The experimental arrangement of main converter and load is made as suggested in [10]. The passive component parameters, operating, and switching frequencies are as per the specifications of Table I. The picture of the hardware is shown in Fig. 9 with major components labeled. The main converter is operated in inverter mode, and the nominal controller gain k r is chosen 10. The conservative choice of k r eliminates any resonance-induced oscillation at the output of the buffer converter. Fig. 10(a) depicts the main converter ac voltage v ac , ac current i a , dc voltage v dc , and input current i s . The peak-topeak second-harmonic ripple in dc voltage is 40 V. The main converter voltages and currents are shown in Fig. 10(b) when the buffer converter is enabled. The ripple in v dc gets reduced to 2 V peak-to-peak, which is a 95% reduction. As expected, the second-harmonic ripple in i s becomes negligible with respect to its average value when the buffer converter is enabled. Reduced second-harmonic (100 Hz) content in i s is shown in the frequency spectrum of Fig. 11(a). The 2χ component in i s reduces from 93% to 8% as the buffer converter is enabled. The residual ripple remains due to active power balance component v * c3,a . The dc bus voltage ripple reduction reflects in the reduced third-harmonic content of i a in Fig. 11(b). The THD of i a improves from 3.3% to 1.7% after the buffer converter is enabled. The remaining third-harmonic component in the output current is attributed to the residual 2χ ripple in the dc bus appearing due to v * c3,a and finite dead time between the gate pulses of top and bottom devices of a switching leg, as discussed in [35].

A. Steady-State Responses
As the main converter does not implement any control for dead-time compensation, 3 rd , 5 th , and higher order harmonics are expected to be present in the ac output. However, this figure highlights that the second-harmonic ripple reduction in the dc bus voltage significantly improves the ac output current THD.

B. Dynamic Responses
1) The dynamic responses of the main converter for k r = 10 are shown in Fig. 12(a)-(c) for unity, 0.866 lagging, and 0.866 leading power factor, respectively. Channel C shows the PWM enable signal for the buffer converter. It is seen that before enabling the buffer converter, the 2χ component in dc bus voltage is significant. As the buffer converter gets enabled, the dc bus ripple becomes negligibly small for both unity and non-unity power factor loads on the main converter. 2) Fig. 12(d) shows the voltage across C 1 captured in inverted and ac coupled mode (−ṽ c1 ). Thus, it principally contains the 2χ ripple. The voltage across C 3 (v c3 ) and dc bus voltage rippleṽ dc are also depicted without and with the buffer converter. Prior to enabling the buffer converter, −ṽ c1 and v c3 were not equal, resulting in 40 V peak-to-peak second-harmonic ripple across the dc bus. When the buffer converter is enabled, −ṽ c1 and v c3 cancel each other, making the dc bus voltage ripple negligible. 3) Fig. 12(e) and (f) depicts the dc bus rippleṽ dc when the main converter load has a step change from R (30 Ω) to parallel R-L load (R || L : R = 30 Ω, L = 80 mH) without and with the buffer converter, respectively. Initially, the current (i L ) drawn by the L load is zero, i.e., the load is purely resistive. This results in the output voltage v ac and current i a being in phase. When the L load is connected, it draws a current i L , which makes i a  to lag v ac . In both the loading conditions, the rippleṽ dc is small for Fig. 12(f) as the buffer converter is enabled. 4) Fig. 12(g) and (h) depict the dc bus rippleṽ dc when the main converter load has a step change from R load (30 Ω) to parallel R-C (R || C : R = 30 Ω, C = 100 μF) without and with the buffer converter, respectively. In both the loading conditions, the rippleṽ dc is small for Fig. 12(h), confirming the desired operation of the buffer converter. 5) Fig. 13

C. Comparison of Response Time
The accuracy of the buffer converter model is verified by comparing the transient response of the analytical model with the response obtained experimentally. Fig. 14(a) shows the analytical response "v c3 (analytical)" and experimentally obtained response "v c3 (experimental)" together. v * c3 is obtained from hardware experiment, filtering the voltage across C 1 through a 2χ BPF. This reference v * c3 , stored in a time-series format, is given as input to the analytical model G pve (s) to compare its response with the experimental response for identical input. A controller gain of 10 is considered for the experiment and also to obtain the closed-loop response of the analytical model. In both experimental and analytical results, v c3 takes eight to ten cycles to track the reference. This shows the consistency between the response times of the analytical model and the experimentally obtained response time when the same reference is given as input.

D. Stability Limit
To demonstrate the stability limit of the buffer converter, k r is increased. Fig. 14(b) shows the voltage across C 3 and the inverted voltage across C 1 in the ac coupled mode. Also, reference signal v * c3 internal to DSP is accessed through DAC with required dc bias and gain for better signal visibility. Resonance oscillation is observed in v c3 when k r = 110, which is close to the stability limit (k critical = 115). The analytical model also predicts this phenomenon at k r = 115. The presence of the resonance frequency component in v c3 is reflected in the dc bus voltage rippleṽ dc , shown in Fig. 14(c). Fig 14(d) depicts the onset of unstable operation when k r is increased from 110 to 115. This is consistent with the stability limit predicted by the root locus in Fig. 8(e).

VII. CONCLUSION
In this work, a detailed model of the SSB that incorporates the loading by the main converter is developed. The model is linearized and simplified based on realistic assumptions to obtain an intuitive second-order model. The model is used to design a voltage-mode controller that facilitates fixedfrequency PWM control of the SSB. The comparison of the performance and stability limits of the controller for the exact and reduced-order model shows a close match. The sensitivity study of the reduced-order model to main and buffer converter parameters indicates the critical nature of C f and R s parameters. It is shown that the effective capacitive load on the buffer converter affects the resonance frequency and damping. The proposed controller design incorporates the limits on the controller parameters and GCF. The experimental results establish the validity of the analytical model and the designed controller. This modeling approach allows the assessment of the stability of the SSB in multiple converter systems sharing a common dc bus, where the effective loading characteristics can vary significantly.

A. Selection of Components and Parameters
For a single-phase H-bridge converter operated with unipolar modulation, analytical expressions for maximum possible peak-to-peak switching ripple is calculated based on the procedure discussed in [36] and [37]. If the ripple in inductor current, ac and dc voltages are to be limited to Δi * L,max , Δv * c,max , and Δv * sw,max , respectively, constraints on the choice of filter parameters are given by (A.1), where V dc , I L , and T s are dc bus voltage, ac current, and switching period of the H-bridge, respectively. The main and buffer converters being H-bridge topologies operated with unipolar sine-triangle modulation, selection of their passive components follow (A.1). The rated and maximum values of the variables pertinent to the design are tabulated in Table VII. Choice of critical parameters are discussed below (A.1) 1) Main Converter-L ac and C f : Using (A.1) and the numerical values in Table VII, L ac is chosen as 1.6 mH (2% of base impedance) to limit maximum peak-to-peak switching ripple in i a to 25% of I a . To limit the maximum peak to peak switching ripple to 1% of the V dc , C f is chosen as 40 μF.
2) Series Stacked Buffer: The design and selection of C 1 , C 2 , and V b parameters are presented in [29], based on an optimal design criteria. The focus of this work is modeling and stability analysis of SSB for fixed frequency modulation, while keeping the design parameters well within the maximum limits C 1,max = 500 μF, C 2,max = 900 μF, and V b,max = 100 V, laid by Liao et al. [29]. Buffer converter is switched at 20 kHz, which is decided based on the main converter switching frequency (10 kHz). a) C 1 : Neglecting the ripple in main dc bus voltage v dc is replaced by V dc . Thus, the modulation index is M m = (V m /V dc ) as provided in Table VII. The maximum modulation index M m,max is considered as 1, taking the load transient, voltage drop in the inductor L ac , and dc source voltage variation into account. When SSB draws the second-harmonic component of i inv , the maximum amplitude of i 2 and v c1,2ω are calculated from (A.2) and tabulated in Considering the maximum limits on the passive parameters, and second-harmonic ripple current and withstand voltage of  RATED CONDITION FOR THE  CONVERTER SPECIFICATIONS GIVEN IN TABLE I the commercially available film capacitors, 200 μF, 500 V film capacitor is chosen. The maximum voltage rating is decided based on the maximum voltage across C 1 keeping a tolerance of ±10% (see Table VII). The ripple current rating of C 1 should be greater than I 2 at 2χ frequency. b) V b and C 2 : The buffer converter applies a secondharmonic voltage across C 3 to cancel the second-harmonic ripple across C 1 , makingv c3 =v c1,2ω . For the buffer converter to operate in linear modulation region (M b < 1), it is necessary that v c2 (t) > v c3 (t). To ensure this, the peak-to-peak 4χ ripple across C 2 is limited to less than 10% of V b , requiring the capacitance C 2 calculated as follows: Neglecting the ripple in v c2 to assume v c2 = V b , which is the average of v c2 , current through capacitor C 2 is found as i c2 (t) = (v c3 (t)i 2 (t)/V b ). Substituting v c2,4ω (t) = V 2 m I 2 m cos (4χt + 2φ) 64χ 2 C 1 C 2 V 2 dc V b = V c2,4ω cos (4χt + 2φ) . (A.5) For peak-to-peak ripple 2V c2,4ω to be less than 10% of V b , the required capacitance C 2 is found to be C 2 > 667 μF. As the energy handled by C 2 depends on the capacitance of C 2 and its average voltage level V b , either a higher C 2 and lower V b (680 μF, 60 V) or a lower C 2 and higher V b (430 μF, 100 V) [10] becomes the feasible choice. It is to be noted that though the capacitance of C 2 is higher than that of C 1 , it is rated for a much lower voltage, which makes its volume smaller than C 1 . c) L b and C 3 : Considering Δi b pk−pk = 20% of I 2 , L b is calculated according to (A.1) An inductor with 305 μH inductance and peak current of 10 A is used as L b . As per (A.1), filter capacitor C 3 = 2 μF ensures peak-to-peak switching ripple in v c3 is limited within 4% of peak of v c3 . Summary of buffer converter parameters are tabulated in Table I.

B. Plant Model Order Reduction Condition
For the circuit parameters tabulated in Table I, the expressions in Table III  The relative values of the circuit parameters in Table I indicate that C 1 C 3 and R s R Ls , even under the worst case of parameter deviations within a range of (±10%). Thus, the expression of a 1 is simplified as Substituting a 1 by b 1 , the plant transfer function G pv (s) is written as G pve (s) in (13). Comparison of the present design and the optimal design [29] parameters and validity of the conditions for plant model order reduction are presented in Table VIII. It shows that, both the proposed and optimal design satisfy the criteria for model order reduction.

C. Parameters of Reduced Order Plant Model
The equivalent capacitance C e and resistance R e are expressed in terms of physical circuit parameters as