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Hardware architecture for high throughput event visual data filtering with matrix of IIR filters algorithm

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posted on 2022-07-06, 21:27 authored by Marcin Kowalczyk, Tomasz KryjakTomasz Kryjak

Neuromorphic vision is a rapidly growing field with numerous applications in the perception systems of autonomous vehicles. Unfortunately, due to the sensors working principle, there is a significant amount of noise in the event stream. In this paper we present a novel algorithm based on an IIR filter matrix for filtering this type of noise and a hardware architecture that allows its acceleration using an SoC FPGA. Our method has a very good filtering efficiency for uncorrelated noise - over 99% of noisy events are removed. It has been tested for several event data sets with added random noise. We designed the hardware architecture in such a way as to reduce the utilisation of the FPGA's internal BRAM resources. This enabled a very low latency and a throughput of up to 385.8 MEPS million events per second.The proposed hardware architecture was verified in simulation and in hardware on the Xilinx Zynq Ultrascale+ MPSoC chip on the Mercury+ XU9 module with the Mercury+ ST1 base board.


The work presented in this paper was supported by the National Science Centre project no. 2021/41/N/ST6/03915 entitled ``Acceleration of processing event-based visual data with the use of heterogeneous, reprogrammable computing devices'' (first author) and partly supported by the programme ``Excellence initiative – research university'' for the AGH University of Science and Technology.


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Submitting Author's Institution

AGH University of Science and Technology

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  • Poland

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