data_synchr_version_3.pdf (552.25 kB)

Hardware design for data synchronization under high interference

preprint

posted on 2022-10-27, 03:22 authored by Dimitris NikolaidisDimitris Nikolaidis

Novel hardware design aimed at capturing data packets under high inteferance.

History

Email Address of Submitting Author

nikolaidisdimitris1994@gmail.com

Submitting Author's Institution

National Technical University of Athens

Submitting Author's Country

Greece

Usage metrics

Categories

Communication, Networking and Broadcast Technologies

Keywords

FPGA-based correlator Packet synchronization Networks High Interference

Licence

Exports