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High-Density Memristor-CMOS Ternary Logic Family

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posted on 03.07.2020 by Xiaoyuan Wang, Pengfei Zhou, Jason Eshraghian, Chih-Yang Lin, Herbert Ho-Ching Iu, Ting-Chang Chang, Sung-Mo Kang
This paper presents the first experimental demonstration
of a ternary memristor-CMOS logic family. We systematically
design, simulate and experimentally verify the primitive
logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance.

Funding

National Natural Science Foundation of China No. 61871429

History

Email Address of Submitting Author

jeshraghian@gmail.com

ORCID of Submitting Author

0000-0002-5832-4054

Submitting Author's Institution

University of Michigan

Submitting Author's Country

United States of America

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