Highly-Parameterised CGRA Architecture for Design Space Exploration of Machine Learning Applications Onboard Satellites

This work presents a highly parameterised CGRA-based accelerator that we developed for an extensive Design Space Exploration activity on design parameters. The description starts from the CGRA building blocks, the Functional Units, and progresses towards the top level of the architecture, represented by the Node component, which is composed of an NxM matrix of Processing Elements. For each level of the hierarchy, we describe the HDL design parameters affecting the run-time reconfigurability of the accelerator, delving deeper into the functionality of the architecture. Outcomes are reported after synthesis on TSMC 40nm standard-cell technology.