Manuscript_wrbae_TCAS1.pdf (1.48 MB)
Download file

In-Memory Hamming Error-Correcting Code in Memristor Crossbar

Download (1.48 MB)
posted on 2021-11-06, 02:43 authored by Woorham BaeWoorham Bae, Jin-Woo Han, Kyung Jean Yoon
This paper proposes a in-memory Hamming error-correcting code (ECC) in memristor crossbar array (CBA). Based on unique I-V characteristic of complementary resistive switching (CRS) memristor, this work discovers that a combination of three memristors behaves as a stateful exclusive-OR (XOR) logic device. In addition, a two-step (build-up and fire) current-mode CBA driving scheme is proposed to realize a linear increment of the build-up voltage that is proportional to the number of low-resistance state (LRS) memristors in the array. Combining the proposed XOR logic device and the driving scheme, we realize a complete stateful XOR logic, which enables a fully functional in-memory Hamming ECC, including parity bit generation and storage followed by syndrome vector calculation/readout. The proposed technique is verified by simulation program with integrated circuit emphasis (SPICE) simulations, with a Verilog-A CRS memristor model and a commercial 45-nm CMOS process design kit (PDK). The verification results prove that the proposed in-memory ECC perfectly detects error regardless of data patterns and error locations with enough margin.


Email Address of Submitting Author

ORCID of Submitting Author


Submitting Author's Institution

UC Berkeley and Ayar Labs

Submitting Author's Country

United States of America