Abstract
Cyclic redundancy check (CRC) is a well-known error detection code that
is widely used in Ethernet, PCIe, and other transmission protocols. The
existing FPGA-based implementation solutions are faced with the problem
of excessive resource utilization in high-performance scenarios. The
padding zeros problem and the introduction of programmability further
exacerbate this problem. In this brief, the stride-by-5 algorithm is
proposed to achieve the optimal utilization of FPGA resources. The
pipelining go back algorithm is proposed to solve the padding zeros
problem. The method of reprogramming by HWICAP is proposed to realize
programmability with a small and constant resource utilization. The
experimental results show that the resource utilization of proposed
non-segmented architecture is 80.7%-87.5% and 25.1%-46.2% lower than
those of two state-of-the-art FPGA-based CRC implementations, and the
proposed segmented architecture has a lower resource utilization by
81.7%-85.9% and 2.9%-20.8% compared wtih the two state-of-the-art
architectures; meanwhile, the throughput and programmability are
guaranteed. We made the source code available on GitHub.