MEMORY CORRECTIONS AND DETECTION USING CRC’s WITH FSM MODELS ON FPGA

Although it's crucial to transport data accurately between two sites since it's needed for some key applications, data transmission errors are surprisingly frequent. Error detection and correction often use the Cyclic Redundancy Check (CRC) approach. In this study, we present a new, hardware-optimized method for error detection and correction in the context of CRC-16, CRC-32, that operates at a comparatively lower power and higher frequency. The suggested method makes it feasible to locate single bit errors precisely and rectify them with the least amount of hardware. This technique saves memory because it doesn't need to look at tables. The effective application of this approach on FPGA is the main topic of this study.