Optimized Pulse Patterns with Bounded Semiconductor Losses

This paper proposes the computation of three-level optimized pulse patterns (OPPs) that achieve not only load-friendly but also converter-friendly operation. To this end, the conduction and switching losses are modeled as a function of the OPP switching angles and the amplitude and phase of the converter current. By minimizing the current harmonics subject to an inequality constraint on the semiconductor losses, OPPs are derived that achieve minimal current distortions with a guaranteed upper bound on the semiconductor losses, thus ensuring the safe operation of the semiconductor switches within their thermal limits. Results for a neutral-point-clamped converter verify the benefits of this approach.