Prediction of Wafer Handling-Induced Point Defects in 300 mm Silicon Wafer Manufacturing from Edge Geometric Data

For the miniaturization of the structures of semiconductor device fabrication, high uniformity of side-flatness and edge roll-off of 300 mm wafers are required. In this study, the formation of light point defects (LPDs) on silicon (Si) wafer surface due to an edge gripper handling system was investigated. The relationships between the generation of LPDs with respect to flatness, edge profile, and edge roll-off of Si wafers were analyzed. It was found that the variation of tradition facet parameters and near-edge geometry metric, such as edge site front surface-referenced least squares/range (ESFQR), have no impact on the formation of surface LPDs. By contrast, the performance of Z-height double derivative (ZDD), allowed an accurate prediction of formation of surface LPDs. Additionally, for a 300mm silicon wafer, the surface LPDs occurred with frontside ZDD obtained at a radius of 149.2 mm, ranging above -954 nm/mm2 . The surface was LPDs free when ZDD was below -1235 nm/mm2. Surface LPD formation occurred randomly and was not predictable when ZDD ranged from -954 nm/mm2 to -1235 nm/mm2. The result indicates that the LPDs caused by wafer handling is proportional to the performance of ZDD at the edge roll-off area of silicon wafer, this is consistent with the requirement of edge roll-off considering wafer geometry.


Introduction
The silicon (Si) wafer properties such as global flatness (bow, warp, total thickness variation (TTV), and global backside ideal range (GBIR)), site flatness (site front surface-referenced least squares/range (SFQR), and nano-topography (NT)), near-edge geometries (edge site front surfacereferenced least squares/range (ESFQR)),and edge roll-off (ERO) parameter, i.e. z-height double derivative (ZDD), are the key product parameters in the manufacturing of polished and epitaxial wafers [1,2], silicon-on-insulator (SOI) [3,4], and other layer conditions, including microelectromechanical systems (MEMS) [5,6] that employ wafer-to-wafer bonding [7,8] and ultrawafer thinning processes [9,10]. Process-induced defects (PIDs) are one of the three types of surface defects (crystal-originated pits, surface-adhered foreign particles, and PIDs) classified in Si wafer manufacturing [11,12]. PIDs are captured as light point defects (LPDs) using commercially available scanning surface inspection systems (SSIS), such as Surf-scan SP5 (KLA, California, USA). The number of LPD captured on the surface areas is a quality indicator of the Si wafers [13,14]. This can be improved by optimizing the wafer manufacturing process such as double-side polishing (DSP), chemical mechanical polishing (CMP) [15,16], and fabrication facilities such as slurry supply system [17,18]. LPD generated by process and metrology equipment during handling [19,20] are inevitable. Consequently, the semiconductor process technology aims to either remove the handling-induced LPDs in the subsequent manufacturing process [21,22], or to ensure the contact points of equipment handling remain at the bevel region of a wafer (Fig. 1). Hence, the measurement equipment in the 300mm semiconductor manufacturing is in contact with the Si wafers only on the exterior of the fixed quality area (FQA). For example, the KLA WS2+ (KLA, Singapore), a widely used geometry measurement equipment for Si wafers, per-forms the measurement while the wafer is held vertically using edge grippers. By contrast, traditional geometry-measurement equipment requires the wafer to be horizontally-held using a vacuum chuck. Gripper design minimizes the impact of gravity on geometry measurement and prevents wafer back-side contamination using chuck contacts [23,24]. However, preliminary investigations based on visual inspection found that edge handling may generate the surface LPDs even when the wafer contact region accessible to edge grippers is less than 0.5 mm from the edge of a wafer. Practically, the edge gripper-caused LPDs occur randomly, resulting yield loss during high-volume manufacturing (HVM). The wafer edge profile is important in determining the actual contact point between the wafer and edge grippers, therefore, the variations in wafer edge profiles may be the root cause of the LPD generation by edge grippers. Furthermore, there are no studies that have reported on the relationship between edge profile and the LPD generation caused by edge grippers. In order to achieve high yield and quality for the semiconductor devices produced from a Si wafer, it is imperative to implement meticulous monitoring and control of the near-edge metric during the manufacturing process. The facets, which pertain to the edges of the wafer, are subjected to chamfering as a preventive measure against chipping or cracking during handling and processing. Hence, the consistent and precise maintenance of high-quality facets through stringent process control is crucial in ensuring reliable and consistent Si wafer production. According to the SEMI standard M73 [25], there are three types of mainstream edges: blunt, blunter, and round type, as shown in Figure 2. The edge profiles can be characterized by facet parameters such as facet lengths A1 and A2, shoulder radii R1 and R2, bevel heights B1 and B2, and bevel angles Ang1 and Ang2 (Fig. 3). The ESFQR [26,27] and ZDD metrics [28] characterize the near-edge geometry from a measured thickness-and height-data arrays, respectively. To determine ESFQR, an annular area is specified along the FQA boundary and divided into sectors (Fig. 4) in contrast to the common rectangular-or square-site pattern used for flatness measurement [29,30]. ESFQR is the difference between the maximum and minimum thickness values for each sector relative to sector thickness least-squares best fit plane. ZDD, a metric for measuring the surface curvature, is measured along the wafer radius, and is a process control tool that quantifies the near-edge curvature of wafers. Figure 5 shows the diagram and equation for calculating ZDD, where R denotes the wafer radius and Z(R) represents the z-height corresponding to the R. The measured data were presented as frontside or backside ZDD depending on the reference plane selected [31,32]. In this study, LPDs caused by wafer handling (edge-gripping) were investigated by using the geometric data measured from the 300 mm Si wafers. The edge profile and near-edge geometry parameters such as edge angle, bevel, apex, ESFQR, and ZDD were examined. The experimental details are discussed in Section 2, the results are discussed in Section 3, and the conclusions are discussed in Section 4. This study aims to verify the possibility of predicting wafer-handling caused point defects using the measured edge geometric data of Si wafers.

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Additive Manufacturing Technologies and Advanced Materials
For this study, 1000 blunt-edged wafers were randomly selected and measured using the WS2+ system, which is the metrology equipment that is widely used in the Si wafer processing, particularly in HVM. Subsequently, all these wafers went through the final-cleaning process followed by a final particle inspection using the SSIS equipment (the KLA SP5). Then, LPD generation was then observed. The selected wafers are single-crystal silicon, p-type, lightly doped, double-side, and mirror polished Si wafers with a diameter of 300 mm, which were manufactured subsequently using the same tool at each process step to ensure that no other interference factors affected the manufacturing process. The specimens were divided into two groups using visual inspection based on surface LPD generation due to the WS2+ grippers. Group 1 consisted of defective wafers with surface LPDs, while Group 2 consisted of non-defective wafers. The wafers in the two groups were compared in terms of the facet (A1, A2, B1, B2, R1, R2) and near-edge geometric (ESFQR, ZDD) parameters. According to the specific contact location between the edge grippers and wafers, the sectors at angle 45 • , 135 • and 270 • were investigated, and are shown in Figure 4. Furthermore, the ESFQR and the facet parameters were measured at the aforementioned angles. A total of 72 sectors with an angular width of 5 • , a radial extension of 35 mm, and edge exclusion of 2 mm were used in determining the ESFQR. The frontside ZDD was measured along the wafer radius ranging from 146 mm to 149.2 mm at an angle of 45 • for both groups. The distance of the LPDs from the wafer edge was measured using a visual inspection tool (Visual Inspection from Innolas Semiconductor GmbH, Germany) and the images were captured using an OLS4000 microscopy tool (Olympus, Germany).

Results and Discussion
In this section, the researchers will delve into an extensive examination of the relationship between LPD, traditional facet parameters, and ESFQR, building upon the results obtained in the previous section. Furthermore, the researchers will explore the correlation between LPD and ZDD, and aim to predict LPD by utilizing the measured ZDD values. These investigations will be conducted based on the established methodologies and outcomes presented in the preceding section.

1. Relationship between LPD, traditional facet parameters, and ESFQR
The facet parameters are shown in Table 1. By comparing the four wafers from Groups 1 and 2, as shown in Figure 6, it was found that no significant difference existed between the two groups in terms of the facet parameters. The facet parameters were close, suggesting that there was no significant difference between the defective and non-defective groups. The ESFQR results, shown in Table 2, are for the sectors that have three contact points located on their surface. Based on these data, there was no correlation between the ESFQR and the defective condition found in both defective and non-defective groups (Fig. 7). Therefore, it can be concluded from this investigation that the selected facet parameters and ESFQR are non-critical factors in near-edge LPD formation.   Table 1.

Relationship between LPD and ZDD
The frontside ZDD values at an angle of 45° along the wafer radius for the three selected wafers are displayed in Figure 8. There was a minor difference between the wafers from Groups 1 and 2 up to a radius of 148.6 mm. The A difference started to gradually increase at 148.8 mm. Significant ZDD deviation was observed at radii of 149 to 149.2 mm. The ZDD difference nonlinearly increased with increasing radius. Hence, the closer the radius was to the wafer edge, the larger the ZDD difference. This trend was also observed with the other two angles, 135 • and 270 • . Furthermore, the impact of frontside ZDD on surface LPD formation due to the edge gripper was also explored in this study: the frontside ZDD @149.2 mm distribution of the 1000 wafers at an angle of 45 • is displayed by category in Figure 9. It was found that LPDs were generated for the specimens with a ZDD above -954 nm/mm 2 (certain defective). For ZDD values below -1235 nm/mm 2 , no LPD were generated by the edge grippers (certain non-defective). The LPDs occurred randomly when the ZDD fluctuated around approximately between -954 nm/mm 2 ∼ -1235 nm/mm 2 (uncertain). This trend was also observed Solid State Phenomena Vol. 345 with the other angles at 135 • and 270 • . These results indicate that the frontside ZDD in the range above -954 nm/mm 2 has an impact on the generation of LPDs due to the edge gripper.

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Predication of LPD by using the measured ZDD values
To further explore the relationship between the LPD location and ZDD values. The wafers from Group 1 with varying ZDD values in different ranges were selected and the LPD distance from the wafer edge was measured using a microscope, as shown in Figure 10: the shadow line represents the wafer edge. The distances from the outermost part of LPD to the wafer edge shown in Fig. 10(a), 10(b), and 10(c) are 106, 130, and 173 µm, respectively. The corresponding values of ZDD @149.2 mm were -1005 nm/mm 2 , -835 nm/mm 2 , and -510 nm/mm 2 , respectively. The results indicated that the distance to the wafer edge increased monotonically as the absolute ZDD value decreased. This is consistent with the aforementioned behavior of LPD formation. The larger the absolute ZDD value, the faster the near-edge flatness slope changed. In this case, the contact area between the wafer and edge gripper significantly reduced, resulting in the edge gripper contact point being confined in the bevel region and absent from the wafer surface area. Other factors such as wafer thickness may also be used in determining the contact point location when ZDD is between -954 nm/mm 2 ∼ -1235 nm/mm 2 , that is, ZDD is no longer a decisive factor in this range, making surface LPD generation unpredictable. Based on the aforementioned results, the edge polishing in the Si wafer manufacturing process should be optimized to maintain a ZDD @149.2 mm within the desirable range (for example, below -1200 nm/mm 2 ) to prevent the near-edge LPD generation due to the edge gripper.

Conclusions
In this study, it established that facet parameters of the wafer edge profile are insufficient in determining whether LPDs are generated by edge grippers. Additionally, near-edge site flatness such as ESFQR was established to have no relation to LPD generation. However, the ERO performance such as frontside ZDD enabled the effective prediction of surface LPD generation at radial measurement positions above 148.8 mm. In particular, at a radial measurement position of 149.2 mm, wafer handling induced LPDs were observed when ZDD above -954 nm/mm 2 , but were not generated for ZDD below -1235 nm/mm 2 . For ZDD in the range -954 nm/mm 2 to -1235 nm/mm 2 , no result was obtained. Other factors such as wafer thickness may also impact LPD generation. Therefore, the larger the absolute frontside ZDD value, the lower would be the probability of LPD generation by the edge grippers. It concludes that the LPD caused by wafer handling is proportional to the performance of ZDD at the ERO area of Si wafer; this is consistent with the requirement of ERO from considering wafer geometry. These results may be applicable to edge-grinding, double-side polishing, and edgepolishing process tuning in the Si wafer manufacturing process.