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Preparation, Imaging, and Design Extraction of the Front-End-of-Line and Middle-of-Line in a 14 nm Node FinFET Device v1.8.pdf (1.45 MB)

Preparation, Imaging, and Design Extraction of the Front-End-of-Line and Middle-of-Line in a 14 nm Node FinFET Device

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posted on 19.08.2021, 01:42 by Adam R. WaiteAdam R. Waite, Yash Patel, John Kelley, Jon Scholl, Joshua Baur, Adam Kimura, Eric Udelhoven, Glen D. Via, Richard Ott, Daniel Brooks
This paper presents the first design reconstruction on the Front-End-of-Line and Middle-of-Line layers of a 14 nm node FinFET design. To accomplish this, a large region of interest within a custom designed 14 nm node ASIC device was delayered, imaged, and analyzed to reconstruct the GDSII design file and verify a 100% match to the golden GDSII design. This work leveraged previous developments in each stage of the front half of the cooperative Verification and Validation (V&V) workflow combined with new techniques and processes developed for processing 3D architecture FET devices. We have demonstrated the critical first step to performing a full V&V workflow on an advanced technology node device, starting from the fabricated silicon device to the design extraction. The process development knowledge gained while reaching this milestone will further accelerate future advancements toward providing trusted advanced technology node devices in a timely manner.

History

Email Address of Submitting Author

waite@battelle.org

ORCID of Submitting Author

0000-0003-2094-3666

Submitting Author's Institution

Battelle Memorial Institute

Submitting Author's Country

United States of America