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Priority Queue VLSI Architecture for Sequential Decoder of Polar Codes

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posted on 21.06.2021, 14:44 by Andrey RashichAndrey Rashich, Aleksei Krylov, Dmitrii Fadeev, Kirill Sinjutin
The VLSI architectures for stack or priority queue (PQ) are required in the implementation of stack or sequential decoders of polar codes. Such type of decoders provide good BER performance keeping complexity low. Extracting the best and the worst paths from PQ is the most complex operation in terms of both latency and complexity, because this operation requires full search along priority queue. In this work we propose a low latency and low complexity parallel hardware architecture for PQ, which is based on the systolic sorter and simplified sorting primitives. The simulation results show that just small BER degradation is introduced compared to ideal full sorting networks. Proposed PQ architecture is implemented in FPGA, the synthesis results are presented for all components of PQ.

Funding

075-15-2020-934

History

Email Address of Submitting Author

rashich@cee.spbstu.ru

Submitting Author's Institution

St. Petersburg Peter the Great University

Submitting Author's Country

Russian Federation