Rapid Admittance Measurement of Power Converters Using Double-PLL Grid-Following Inverters

The increasing use of inverter-based resources (IBRs) in power systems highlights the need for a deep understanding of their stability and dynamics. Traditional analytical models, limited by the black-box nature of IBRs, underscore the importance of frequency-domain methods through measured admittance. Facing challenges in real-world admittance measurement, such as the absence of ideal voltage or current sources, the use of measurement inverters as perturbation sources has emerged as a promising approach, despite drawbacks like reduced system stability and increased measurement time. This article introduces a novel control strategy for measurement inverters, elucidating the impact of abc/dq and dq/abc transformations on admittance measurement. The key advancements are an analysis of the admittance contributions from these transformations and the implementation of double phase-locked loops in the measurement inverters, aimed at improving stability and decreasing measurement duration.


I. INTRODUCTION
I N THE evolving landscape of power systems, inverter-based resources (IBRs) are progressively gaining prominence as they gradually replace traditional synchronous generators [1].This paradigm shift necessitates an in-depth examination of the stability and dynamic behavior alterations within these IBR-dominated power systems.Analytical models present an intuitive solution to explore these changes [2], [3].However, a significant obstacle emerges due to these IBRs' black-box feature posed by the intellectual property constraints, which calls for the admittance measurement technology [4], [5].
Mohammad Hasan Ravanji is with the Department of Electrical Engineering, Sharif University of Technology, Tehran 14588-89694, Iran.
Color versions of one or more figures in this article are available at https://doi.org/10.1109/TPWRD.2024.3363762.
Digital Object Identifier 10.1109/TPWRD.2024.3363762point of common coupling (PCC) to estimate admittance without introducing system perturbations.The process of admittance estimation in these methods eliminates the need for discrete Fourier transform (DFT) post-processing of voltage and current signals.Moreover, these methods are non-intrusive, thus avoiding stability issues associated with external measurement devices.However, their major drawback is often lower accuracy [6], [7].
Using active methods for admittance measurement within simulation environments, such as electromagnetic transient platforms like PSCAD or Matlab/Simulink, is relatively straightforward [13], [14], [15], [16].For example, ideal three-phase controlled voltage or current sources can readily generate and inject perturbation signals, facilitating the precise measurement of the inverter impedance.Yet, translating this simulation tool into realworld experimental equipment presents substantial challenges, primarily because the ideal voltage or current sources have no physical counterparts.
In real-world experiments, various devices serve as sources for perturbation generation and injection.These include woundrotor induction machines with three-phase chopper circuits [17], single-phase chopper circuits [18], power amplifiers [19], [20], frequency response analyzers [21], and generators [22], [23].Specifically, a current perturbation generated by a three-phase chopper circuit is added to the DC current reference of a wound rotor induction machine in [17].A simplified and less-costly perturbation injection scheme is presented in [18], where an interphase multi-tone unbalanced sinusoidal perturbation signal is generated using a single-phase H-bridge or chopper circuit and injected between two phases.A bulky customized three-phase impedance analyzer composed of a real-time microcontroller and three linear power amplifiers is constructed in [19] and further employed in [20].Three-phase voltage perturbations are injected by a frequency response analyzer in [21] to measure the inverter's impedance considering the frequency coupling effect.A generator is connected in series with the inverter in [22], [23] to supply operating voltage while injecting a multi-tone sinusoidal voltage perturbation.Although these dedicated devices can accurately measure the inverter's impedance, they either are expensive or cumbersome to handle.For instance, the authors recently received a quote from Venable Company for the Venable 7405 frequency response analyzer, as employed in [21], pricing it at over forty thousand USD.
An effective and feasible approach involves utilizing another inverter as the perturbation source [24], [25], [26], [27].Compared to the aforementioned devices, inverters provide much easier management due to their superior control flexibility.To enhance clarity, grid-following inverters (GFLIs) used for power conversion are termed Power GFLI (PGFLI) and those for admittance measurement as Measurement GFLI (MGFLI), respectively, in this article.Specifically, impedance frequency responses of a three-phase RL load and a six-pulse diode rectifier are measured in [24] by a three-phase-MGFLI-based impedance measurement unit.The PGFLI sequence impedance is measured in [25] using a paralleled grid-forming inverter with a similar power rating to the PGFLI under test.The measurement setup is simple without any additional AC source or load bank.An impulse signal is injected into the duty cycle of a paralleled MGFLI in [26], where only the parametric grid resistance and inductance instead of PGFLI impedance are measured.The coupling effect of grid impedance on the impedance measurement accuracy is analyzed in [27], where the MGFLI's effect is ignored.Furthermore, the stability effects of these additional inverters on impedance measurement are not investigated in [24], [25], [26], [27].
To rectify the aforementioned issues, the current feed-forward and voltage feedback are employed in [28] to reshape the MGFLI impedance so that its adverse stability effect on impedance measurement can be mitigated.However, the stability effect of the MGFLI's phase-locked loop (PLL) is not considered in [28].The PLL in the MGFLI detects the voltage phase angle at the perturbation point, enabling precise injection of three-phase perturbations into the d-axis and q-axis.It also extracts d-axis and q-axis components from the response, essential for computing dq-axis admittance by dividing current perturbations/responses by the corresponding voltage responses/perturbations [19], [20], [24], [27], [28], [29], [30], [31].
The PLL's influence on the admittance measurement is analyzed in [29], [30], [31].It is shown that the dynamic of the phase angle used for the admittance calculation instead of that for the perturbation injection of the MGFLI has a significant influence on the admittance measurement accuracy.To mitigate the PLL's effect, a correction method is developed in [29] based on the analytically derived PLL transfer function, and an improved admittance calculation method is developed in [30].Also, an additional low-bandwidth PLL is adopted in [31] to post-process the measured signals.However, all of these approaches act as after-the-fact corrections and do not change the control strategy of the MGFLI, thus not fundamentally eradicating its PLL's negative impact on admittance measurement.
To navigate these multifaceted challenges, this article presents a pioneering alternative control strategy for the MGFLI.An analytical exploration of the MGFLI's admittance elucidates the influence of the abc/dq and dq/abc transformations on the MGFLI's admittance.By employing a slow PLL and a fast PLL for the two transformations, the system stability and dynamics can be simultaneously preserved, thus reducing measurement time.The significant contributions of this article are thus twofold.First, uncovering that the abc/dq transformation has no admittance contribution under zero power injection conditions, whereas the dq/abc transformation has a non-negligible admittance contribution and can degrade system stability.Second, the development of double PLLs for the MGFLI to ensure a harmonious balance between stability and response speed, thus reducing admittance measurement time.
The remainder of this article is structured as follows.In Section II, the issue of the admittance measurement using the single-PLL MGFLI is shown and analyzed.Double PLLs are proposed in Section III for the MGFLI.Section IV provides the performance evaluation.Section V concludes this article.

II. ADMITTANCE MEASUREMENT USING SINGLE-PLL MGFLI
In this section, the admittance measurement using the conventional single-PLL MGFLI is first explained.The effect of its PLL bandwidth on the system's dynamic performance and stability is then shown and theoretically explained.

A. Admittance Measurement Configuration
Fig. 1 shows the configuration of the admittance measurement system, which comprises an MGFLI and a PGFLI connected in parallel to the PCC.The only difference between the MGFLI and PGFLI under study is that the MGFLI serves as the power amplifier of the dq-domain small-value sinusoidal current reference i pert,ref 1dq , whereas the PGFLI serves as the power amplifier of the dq-domain large-value DC current reference.The superscript m denotes matrix, while the superscripts pert and resp denote perturbation and response, respectively.The superscripts s and c denote that the variables are represented within the system and controller reference frames, respectively.The MGFLI is connected to the PCC via an L filter with the inductance L f1 and the parasitic resistance R f1 .The alternating current control (ACC) is equipped with a PI controller G acc with a dq-axis decoupling term G m dec [3].A synchronous reference frame (SRF)-PLL with a PI controller G pll is employed to track the phase angle of the voltage at the admittance measurement point, θ 1 .In addition, a first-order low-pass filter (LPF) G ilpf is used to eliminate the high-frequency current measurement noise.
The circuit and controller parameters of the MGFLI and PGFLI can be found in Table 1.The base power is selected as 300 kVA, and the base voltage is selected as the phase-to-phase Vrms 575 V, leading to a base current and base impedance of 4264 A and 0.11 Ω, respectively.The grid is purely inductive, and its short-circuit ratio is 5.

B. Limitations of the Admittance Measurement Using the Single-PLL MGFLI
To demonstrate the impact of the MGFLI's PLL bandwidth on the stability and dynamic performance during the admittance measurement procedure, three case studies for the system of Fig. 1 are conducted in Matlab/Simulink environment with the parameters given in Table 1: Case #1 representing a system with a very low PLL bandwidth of 0.697 rad/s, Case #2 adopting a PLL with a bandwidth of 6.97 rad/s, and Case #3 equipped with a higher PLL bandwidth of 34.85 rad/s.Fig. 2 shows that Case #1 needs a long time of more than 200 s to reach the steady state.In addition, after the onset of the perturbation, a 0.4-Hz frequency component emerges before 50 s and disappears at 200 s.Fig. 2(c) shows that Case #1 requires at least 100 s for admittance measurement.Fig. 3 shows that, compared to Case #1, Case #2 needs a much shorter time of about 50 s to reach the steady state, whereas the 0.4-Hz frequency component emerges before 100 s and disappears at 300 s.Fig. 3(c) shows that Case #2 requires at least 200 s for admittance measurement.Fig. 4 shows that further elevating the PLL bandwidth to 34.85 rad/s results in an unstable system, with the 0.4-Hz frequency component persisting.Consequently, the admittance measurement scheme proves unviable in this high PLL bandwidth scenario.These three case studies underscore the critical interplay between the MGFLI's PLL bandwidth, dynamics performance, and system stability.The stability degraded by the MGFLI's high PLL bandwidth is explained in the next subsection.

C. Stability Degradation Induced by Single-PLL MGFLI 1) Stability Degradation Explained by the Admittance:
The analytical input admittance of the single-PLL MGFLI is derived in Appendix B and is presented by (17) , has a 0.4-Hz magnitude peak where the phase angle jump is smaller than 180 • , indicating that the time-domain waveform should have a damped 0.4-Hz transient frequency component [34], which matches the simulation results in Fig. 3.However, when the MGFLI has a 34.85-rad/sPLL bandwidth, the Z m whole has a 0.4-Hz magnitude peak where the phase angle jump is larger than 180 • , indicating that the timedomain waveform should have an undamped 0.4-Hz frequency component [34], which matches the simulation results in Fig. 4. As a comparison, Fig. 5 also shows that the Bode diagram of the whole-system impedance Z m whole in Fig. 1 without considering the MGFLI, i.e., (Y m pgfli + Y m g ) −1 , has a 0.7-Hz magnitude peak where the phase angle jump is smaller than 180 • , indicating that the system should be stable with a well-damped 0.7-Hz transient frequency component.
2) Stability Degradation Explained by Eigenvalues: Fig. 6(a) establishes the block diagram for G vpll± and  G ipll± shown in (13) in Appendix C, which can be modeled as and According to Fig. 19(a), the state-space model (SSM) of the single-PLL MGFLI can be derived by combining (1), (2), and the state-space representations of G ilpf , G acc , G del , G L , and G dec shown in (12) in Appendix B. By inserting a large virtual parallel resistor such as 1 MΩ at the PCC in Fig. 1, the SSMs of the single-PLL MGFLI, PGFLI, grid, and the virtual resistor can be combined to derive the whole-system SSM.Fig. 6(b) shows the whole-system's critical eigenvalue loci of Fig. 1 as the MGFLI's PLL bandwidth ω pll mglfi increases from 0.697 to 139.4 rad/s with the step size of 6.97 rad/s, indicating that, the critical eigenvalue pair c 1,2 moves rightward as PLL bandwidth ω pll mgfli increases, leading to decreased stability margin and even instability.Specifically, when ω pll mgfli is larger than 28.577 rad/s, c 1,2 having ±0.4-Hz imaginary part are within the right-half plane, which matches Figs. 2, 3, 4, and 5(b).As a comparison, without the MGFLI, the critical eigenvalue pair A 1,2 (−1.1, ±2π0.66) is located within the left-half plane and matches the 0.7-Hz magnitude peak in Fig. 5(b).
It should be noted that this section investigates the stability and dynamic implications of the PLL in scenarios characterized by minimal to zero power transfer, diverging from the common focus on PLL-induced challenges in high-power scenarios where power transfer can reach up to 1 p.u., as discussed in previous research [20].

III. ADMITTANCE MEASUREMENT USING THE PROPOSED DOUBLE-PLL MGFLI
In this section, a double-PLL approach is proposed for the MGFLI to simultaneously preserve stability and improve dynamic performance.The SSM and admittance model of the proposed double-PLL MGFLI are then derived to verify stability and dynamic performance.

A. Proposed Double-PLL MGFLI
In this subsection, the contributions of the abc/dq and dq/abc transformations to the MGFLI's input admittance are analytically derived.It is then concluded that, under zero current injection conditions, a high PLL bandwidth only negatively impacts the dq/abc transformation's admittance contribution, whereas the abc/dq transformation's admittance contribution remains unchanged.Therefore, the dq/abc and abc/dq transformations are equipped with two separate PLLs, one slow and one fast, to simultaneously guarantee stability and improve dynamic performance.
To analytically derive the admittance contributions of the two transformations, the single-PLL MGFLI's small-signal model derived in Appendix B is used.Specifically, Δi pert,s 1dq4 and Δi pert,s 1dq5 shown in (19) in Appendix B is reformulated as and respectively, where tf pll = G pll /(s + G pll ).In addition, Y m #2dq/abc and Y m #1abc/dq denote the #2 dq/abc and #1 abc/dq transformations-induced admittance components, respectively.Since I 1d and I 1q are 0 p.u. for the MGFLI, one can write that which indicates that #1 abc/dq transformation does not contribute to the MGFLI's input admittance no matter how large the PLL bandwidth is, whereas #2 dq/abc transformation can affect dq-and qq-axis components via tf pll .The MGFLI's input admittance Y m mgfli in ( 17) can be reformulated using (19) as Fig. 7 shows the Bode diagrams of tf pll and 1-tf pll at 1 Hz, indicating that, as PLL bandwidth ω pll mgfli increases, the magnitude of tf pll increases to 1, and its phase angle increases from −90 • to 0 • , whereas the magnitude of 1-tf pll decreases from 1 to 0 and its phase angle increases to 180 • .According to (6), the frequency range where the phase angle of the qq-axis component of Y m mgfli is higher than 90 • becomes wider as PLL bandwidth increases, since the phase angle of the qq-axis component of Y accm cl is already about 90 • [3].In summary, to maintain the system's stability, the MGFLI's #2 dq/abc transformation should employ a slow PLL, whereas there is no PLL bandwidth requirement for #1 abc/dq transformation.Therefore, a much faster PLL can be employed for #1 abc/dq transformation to improve the dynamic performances.
Fig. 8, based on the above analysis, implements a fast PLL for #1 abc/dq transformation and a slow PLL for #2 dq/abc transformation, i.e., G pll1 = K ppll1 + K ipll1 /s of the PLL #1 is larger than G pll2 = K ppll2 + K ipll2 /s of the PLL #2.

B. Admittance and State-Space Modeling of the Proposed Double-PLL MGFLI 1) Admittance Modeling of Double-PLL MGFLI:
The single-PLL MGFLI's small-signal model shown as Fig. 19(a) Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply. in Appendix B is reformulated as Fig. 19(b) to derive the dq/abc transformation's small-signal dynamics, i.e., G mpll± in (22).Considering further that G ipll± in (13) represents the abc/dq transformation's small-signal dynamics, the employments of G pll1 for the abc/dq transformation and of G pll2 for the dq/abc transformation in Fig. 8 makes G mpll± and G ipll± become and respectively.Substituting for G mpll± from (7) and G ipll± from (8) into (21) leads to (9) shown at the bottom of this page.
If G pll1 = G pll2 = G pll , G vpll± in ( 9) and ( 13) are the same, indicating that the double-PLL approach is a generalized implementation of the single-PLL one.The admittance model of the double-PLL MGFLI can be obtained by substituting for G ipll± from ( 8) and G vpll± from ( 9) into (17).Fig. 9 shows the Bode diagram of the proposed double-PLL MGFLI's input admittance when PLL bandwidth of #1 abc/dq transformation ω pll1 mgfli or of #2 dq/abc transformation ω pll2 mgfli increases from 6.97 to 69.7 rad/s, indicating that increasing ω pll1 mgfli does not affect the input admittance, whereas increasing ω pll2 mgfli can widen the qq-axis non-passive frequency region, which matches the insights provided by (5).
2) State-Space Modeling of Double-PLL MGFLI: Fig. 10(a) establishes the block diagram for G vpll± shown in (9), which  2), (10), and the state-space representations of G ilpf , G acc , G del , G L , and G dec shown in (12) in Appendix B. Note that K ppll and K ipll in (2) should be updated as K ppll1 and K ipll1 , respectively.By inserting a large virtual parallel resistor such as 1 MΩ at the PCC in Fig. 1, the SSMs of the double-PLL MGFLI, PGFLI, grid, and the virtual resistor can be combined to derive the whole-system SSM.mgfli increases from 0.697 to 139.4 rad/s with step size of 6.97 rad/s and PLL #2's bandwidth ω pll2 mgfli is kept as 0.697 rad/s, indicating that the low-frequency stability can be guaranteed with the help of the proposed double PLLs.
Additionally, Fig. 11 shows the measurement-point voltage detected by the double-PLL MGFLI, which indicates that the q-axis voltage v pu 1q reaches the steady state more quickly if a faster PLL #1 is employed, indicating that the system dynamics can be improved with the help of the proposed double PLLs.It can be concluded from Figs. 10 and 11 that the proposed double-PLL MGFLI may reduce the measurement time since the system stability is guaranteed and system dynamics performance is improved.

IV. PERFORMANCES EVALUATION
In this section, the performances of the proposed double-PLL MGFLI for admittance measurement are evaluated using both the simulation and experimental results.

A. Simulation Results
In this subsection, the performances of the proposed double-PLL control strategy for the MGFLI are evaluated in a simulation environment.The system described in Fig. 1 with the parameters given in Table 1 is simulated in MATLAB/Simulink.To evaluate the performances of the proposed double-PLL MGFLI and to contrast it with the existing method, the impedance of the PGFLI is estimated by adopting the impedance measurement procedure shown in Section II-A.
1) Stability Guarantee and Dynamics Improvement: To contrast the performance of the proposed method with that of the single-PLL one, a test identical to those in Section II-B is repeated for the same system while the single-PLL MGFLI is replaced by a double-PLL one.The bandwidth of PLL #1 is ω pll1 mgfli 6970 rad/s, and that of PLL #2 is selected as ω pll2 mgfli 0.697 rad/s.The rest of the parameters remain unchanged.Figs.12(a   2) Admittance Measurement Time Reduction: In this test, using the simulation results of the previous test and the tests conducted in Section II-B, the admittance of the PGFLI is estimated for the three different scenarios and is compared with the theoretical admittance Y m pgfli derived in (17) in Appendix B. The admittance is estimated by performing the DFT on the PCC voltage and the PGFLI output current before 50 s for Case #1 in Fig. 2, Case #2 in Fig. 3, and using the double-PLL MGFLI in Fig. 12. Fig. 13 depicts the admittance measurement results calculated by (11).Compared to Cases #1 and #2, the admittance measured by the double-PLL MGFLI is more accurate and highly agrees with the PGFLI's theoretical admittance model Y m pgfli .Additional investigations show that for Cases #1 and #2, to achieve the same measurement accuracy level of the proposed method, about 100-s and 200-s measurement data must be used, respectively.The proposed double-PLL MGFLI can thus help reduce the required measurement time.

B. Experimental Results
In this subsection, the performances of the proposed double-PLL MGFLI and the conventional single-PLL MGFLI in terms of maintaining system stability while their PLL bandwidths are increased are experimentally evaluated.To this end, an experimental setup, as shown in Fig. 14, with the same structure as Fig. 1 is utilized.The experimental setup consists of two DC sources, a Regatron grid simulator, and two Imperix inverters controlled by a BoomBox Imperix Controller.The two Imperix inverters are SiC-based two-level three-phase inverters.In addition, the BoomBox controller is a fully programmable control platform that can be programmed using either C or directly from Matlab/Simulink.The parameters of this setup are presented in Table 2.    q-axis current references for the PGFLI are 0.71 p.u. and 0 p.u., respectively.As shown in Figs.15(a) and (b), the system stability is degraded as the PLL bandwidth of the single-PLL MGFLI is increased from 20.91 rad/s to 104.55 rad/s, which confirms that the MGFLI can deteriorate the system stability even under almost zero power injection condition if its PLL bandwidth is sufficiently large.
Figs. 16(a) and (b) show the experimental results of the PGFLI output current and the MGFLI output current, respectively, when the proposed double-PLL MGFLI is used.In this test, the MGFLI's PLL #2's bandwidth, ω pll2 mgfli , is fixed at 20.91 rad/s, and PLL #1's bandwidth, ω pll1 mgfli , is increased from 209.1 rad/s to 1045.5 rad/s.The PLL bandwidth of the PGFLI is fixed at 69.7 rad/s.Fig. 16 shows that system stability can be guaranteed even if a large bandwidth is used for PLL #1.
To further substantiate that the dq/abc transformation indeed impacts system stability, Figs. 17  mgfli , is fixed at 20.91 rad/s, and PLL #2's bandwidth, ω pll2 mgfli , is increased from 20.91 rad/s to 104.55 rad/s.The PLL bandwidth of the PGFLI is fixed at 69.7 rad/s.Fig. 17 demonstrates that employing a large bandwidth for PLL #2 can lead to system stability deterioration, even in scenarios where the MGFLI operates under zero power injection conditions.
V. CONCLUSION This article investigates the impact of using a single PLL in an MGFLI for wideband current perturbation injections to measure the admittance of a PGFLI.Findings reveal that low-frequency stability can be compromised in the system, even with minimal power injection from the MGFLI.This challenge can result in longer admittance measurement periods; for instance, in our case study, the time required expanded from 100 s to 200 s when the single PLL's bandwidth was increased from 0.697 rad/s to 6.97 rad/s.In more severe scenarios, this could result in system instability.The primary cause of this stability degradation is identified as the dq/abc transformation in the MGFLI's control scheme.To address this, a fast PLL for the abc/dq transformation and a slower PLL for the dq/abc transformation are proposed, aimed at maintaining low-frequency stability while enhancing dynamic performance and reducing admittance measurement time.The effectiveness of the double-PLL MGFLI approach is validated through admittance analysis, eigenvalue analysis, simulations, and experiments.Exploring the broader potential of the double-PLL concept, particularly in enhancing the maximum transferable active power of GFLIs under weak grid conditions, is a promising direction for future research.

APPENDIX A ADMITTANCE MEASUREMENT USING MGFLI
Figs. 18(a) and (b) illustrate the d-and q-axis current perturbation generation principles, respectively, for the MGFLI.In the steady state, the PLL-defined controller reference frame (d c , q c ) and measurement-point voltage v 1abc -defined system reference frame (d s , q s ) are overlapped, hence v c 1dq = v s 1dq .When i pert,ref is excited with a given frequency, both d-and q-axis steady-state currents contain the same frequency component due to the coupling effect between the two axes.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.Two rounds of three-phase current perturbations, i pert 1abc , are sequentially injected at the PCC as illustrated in Fig. 1, following the methods outlined in Figs.18(a) and (b).Concurrently, the three-phase PCC voltage responses, v 1abc + v resp 1abc , and the three-phase PGFLI current responses, −i 1abc + i pert2 1abc , for both perturbation rounds are recorded.Utilizing a PLL, these responses are transformed into the dq-domain, resulting in v resp,s 1dq,1st , v resp,s 1dq,2nd , i pert2,s 1dq,1st , and i pert2,s 1dq,2nd .From these dq-domain responses, the admittance frequency responses of the PGFLI, Y m pgfli , can be calculated as where the superscript mgfli indicates that the admittance frequency responses are measured by the MGFLI.In addition, F() denotes the DFT operator.

APPENDIX B SMALL-SIGNAL MODEL OF THE SINGLE-PLL MGFLI
In this section, the small-signal model of the single-PLL MGFLI is derived and reformulated.

A. Derivation of the Small-Signal Model
The small-signal model of the single-PLL MGFLI in Fig. 1 is shown in Fig. 19(a), where G ilpf , G acc , G dec , G del , and G L are the complex-valued transfer functions of the LPF, ACC, decoupling term, delay, and L filter, respectively, expressed by In addition, G vpll± and G ipll± are the complex-valued transfer functions of the PLL, shown as By comparing ( 14) and (19), it is clear that Δi pert,s 1dq2 + Δi pert,s 1dq3 = Δi pert,s 1dq4 + Δi pert,s 1dq5 , (20) which leads to Substituting for G vpll± and G ipll± from ( 13) into (21) yields which depicts the small-signal dynamics of the #2 dq/abc transformation, and is used in Section III-B to derive the small-signal model of the proposed double-PLL MGFLI.

APPENDIX C THE SMALL-SIGNAL MODEL OF FIG. 10(A)
A vol db,pll -D vol db,pll in (10) are as follows.

Manuscript received 10
September 2023; revised 13 December 2023; accepted 1 February 2024.Date of publication 8 February 2024; date of current version 23 May 2024.This work was supported by the Australian Renewable Energy Agency under Grant 2020/ARP007 and Grant 2023/ARP010.Paper no. TPWRD-01239-2023.(Corresponding author: Weihua Zhou.) 4. The PGFLI's active and reactive current references, i ref 1d and i ref 1q , are 1 and −1 p.u., respectively.The MGFLI's current reference i pert,ref 1dq includes 298 frequency Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

Fig. 1 .
Fig. 1.Single-line diagram of the admittance measurement system using the single-PLL MGFLI.

Fig. 5 (
a) shows the Bode diagram of this input admittance matrix, Y m mgfli , which indicates that, although the MGFLI's current injection is almost zero, the frequency region where the qq-axis admittance's phase angle is outside [−90 • , 90 • ] can still exist and becomes wider when its PLL bandwidth ω pll mgfli increases.Fig. 5(b) shows that, when the MGFLI has a 6.97-rad/s PLL bandwidth, the Bode diagram of the whole-system impedance Z m whole in Fig. 1, i.e., (Y m mgfli

Fig. 10 (
Fig. 10(b), different from Fig. 6(b), shows that the whole system's critical eigenvalue pair c 1,2 keeps constant when PLL #1's bandwidth ω pll1mgfli increases from 0.697 to 139.4 rad/s with step size of 6.97 rad/s and PLL #2's bandwidth ω pll2 mgfli is kept as 0.697 rad/s, indicating that the low-frequency stability can be guaranteed with the help of the proposed double PLLs.Additionally, Fig.11shows the measurement-point voltage detected by the double-PLL MGFLI, which indicates that the q-axis voltage v pu 1q reaches the steady state more quickly if a faster PLL #1 is employed, indicating that the system dynamics can be improved with the help of the proposed double PLLs.It can be concluded from Figs. 10 and 11 that the proposed double-PLL MGFLI may reduce the measurement time since the system stability is guaranteed and system dynamics performance is improved.
) and (b) show the simulation results of the PCC voltage v c 1dq + v resp,c 1dq and the PGFLI output current i c 1dq − i pert2,c 1dq , respectively, when
(a) and (b) show additional experimental results of the PGFLI output current and the MGFLI output current, respectively, when the proposed double-PLL MGFLI is used.In this test, the MGFLI's PLL#1's bandwidth,

where 1 +
Fig. 19(a) is reformulated as Fig. 19(b), from which it can be derived that

TABLE I PARAMETERS
OF THE PGFLI AND MGFLI IN SIMULATION components logarithmically distributed within [1, 2500] Hz, and each frequency component has a magnitude of 0.1/298 p.u.The methodology for admittance measurement utilizing the MGFLI is detailed in Appendix A.