Reference Spur Reduction in Sampled-loop filter PLLs by Oversampling

A technique to eliminate reference spurs in both Integer-N and Fractional-N charge pump phase locked loops(PLLs) based on an oversampled loop filter architecture is proposed. A detailed analysis of the performance of the proposed technique in the presence of implementation non-idealities is also presented. It is shown through analysis and simulations that the proposed technique, in addition to completely eliminating reference spurs, adds an insignificant area and power overhead when applied to Integer-N PLLs and less than 6% increase in area and power in case of Fractional-N PLLs.


I. INTRODUCTION
One of the major problems in charge pump PLLs is reference spurs which arise from its periodic sampling nature in the presence of phase frequency detector (PFD) and charge pump (CP) non-idealities [1], [2], [3], [4], [5], [6]. Reference spurs increase period jitter and out of band emissions of the PLL and to filter these spurs, the bandwidth of the PLL is reduced. A reduced bandwidth results in poor rejection of VCO Phase noise and an increased settling time. Hence reducing reference spurs is a major concern when designing wide bandwidth PLLs. One popular approach to reduce reference spurs in CP-PLLs is the sample-reset loop filter (SLF) technique [3], [6], [7], [8] shown in Fig.1. By sampling the charge injected from CP onto a sampling capacitor (C s ) and then deliver the charge to the loop filter Z(s), after a delay T D (when the CP current i cp (t) is zero), the loop filter (and the VCO) does not 'see' the sudden voltage variations caused by the transient CP current. Thus the reference spurs are reduced in a SLF PLL. However the charge injection from the sampling switch in the SLF-PLL can still produce significant reference spurs. Using dummy switches alongside the actual sampling switch can reduce the reference spurs to some extent. Since this relies on circuit techniques, a complete elimination is not practically feasible due to device mismatches. In this work a simple technique to completely eliminate reference spurs in SLF-PLL by using a sampling clock of higher frequency is proposed. The proposed technique, when applied to Integer-N PLLs eliminates reference spurs without any additional area or power overhead and in the case of Fractional-N PLLs, with a marginal increase ( < 6 %) in area and power. Section II discusses the proposed technique in Integer-N and Fractional-N PLLs. A detailed analysis and comparison of spur levels before and after applying the technique is discussed in Section III. Section IV presents the test bench and the simula- II. REFERENCE SPUR REDUCTION BY OVERSAMPLED LOOP FILTER (OSLF) TECHNIQUE The source of reference spurs in SLF PLL is the periodic charge injection from the sampling switch into the loop filter. The proposed solution in this work is to increase the frequency of the sampling switch control signal by M times the reference frequency. By doing so, the reference spurs will be absent upto M f r . The problem now, is to derive the high frequency switch control signal Sos without adding much to the complexity or power consumption of the PLL.

1) Integer-N PLLs:
In case of Integer-N PLLs, the VCO frequency is an integer multiple of the reference frequency ( f vco = N f r ). Therefore the higher sampling frequency clock M f r can be derived from the VCO clock using a frequency divider. But adding an additional divider increases the power consumption as it operates at the VCO frequency. So the feedback divider can be split into two parts and the high frequency signal can be derived from the feedback divider path as shown in Fig.2. The divider is split into N 1 and M. The value of N 1 can be computed as 2) Fractional-N PLLs: In case of Fractional-N PLLs, one possible approach to generate the high frequency sampling  To avoid the aforementioned problems, the oversampling clock M f r is derived from the reference clock directly using a frequency multiplying PLL (MPLL) as shown in Fig.4. The jitter of the MPLL is not a major concern (as it only affects the sampling instant and not the charge injected into the loop filter) and hence the MPLL can be realised with much lower power (using ring oscillator based VCO) and smaller area compared to the Fractional-N PLL 1 . The OSLF technique is used in the MPLL as well to ensure the oversampling signal M f r does not contain any reference spurs. The output of the MPLL is chosen to be twice the oversampling frequency f mvco = 2M f r , so that the signal S os has a 50 % duty cycle.

3) Choosing the delay T D :
The delay should be chosen such that the signal S os is 'low' at the beginning of the 1 Another point to note is that the MPLL output can in theory be used as a reference input to the Fractional-N PLL there by removing the reference spurs upto M f r (and even reducing the Σ − ∆ noise). However this approach has two major problems 1) The power of the PLL increases as the Σ − ∆ modulator operates at M f r and 2) The MPLL clock is very noisy and this will significantly increase the in-band noise of the Fractional-N PLL. Then the signal S os should be delayed by T D seconds such that T D > ∆ max . Furthermore, since the frequency of the signal S os is much higher than the reference frequency, it should be ensured that the off-time of S os , T o f f = T /2M > ∆ max + T m , where T m is an additional time margin given to ensure that S os does not go 'high' in that region. This condition puts an upper limit on the value of M. In case of Integer-N PLLs, the delay T D can be rounded-off to the nearest integral multiple of 0.5T vco and realised using a series of flip flops clocked at the alternate edges of VCO clock as shown in Fig.5.(b). The output of the flip-flops change at the oversampling frequency of M f r and the power consumed in the delay element will be a small fraction of the frequency divider (N 1 in Fig.2) in the feedback path. In case of Fractional-N PLLs the steady state phase error is much higher in comparison to Integer-N PLLs. The delay T D can be realised in a much simpler way by exploiting the multistage ring oscillator in the MVCO. In this work, the MVCO is designed as a four stage differential ring oscillator running at 2M f r and thus the oversampling clock M f r can be delayed in steps of T /16M. The delay T D can be rounded off to the nearest multiple of T /16M and then realised using a single flip-flop clocked by one of the eight appropriate phases (φ x ) of the MVCO as shown in Fig.5.(c). The same sampling signal can be used in the MPLL as well to save power. It is instructive to compare the highest spur level in OSLF with the reference spur at f r in the SLF technique. The charge injection current can be modeled as two impulses of opposing polarity spaced T on seconds apart as shown in Fig.6. In both SLF and OSLF technique the duty cycle of the switch control signal S/S os is chosen to be 50 %. Incase of SLF technique T on = T /2 and in case of the OSLF technique T on = T /2M. This is done to ensure that the average ON resistance of the switch is same in both the techniques [9] and also the even harmonics will be absent in spectrum. The spectrum of the injected current into the loop filter impedance Z(s) in case of the SLF and OSLF technique is given by The reference spur at the PLL output can be shown to be [1], [2], [3], [4] S φ (k f r ) = 10 log 10 The highest spur level difference in both the techniques can be computed from Eq.(2), Eq. (3) and Eq.(4) where P = N p − N z is the difference between the number of poles (N p ) and zeroes (N z ) of the impedance Z(s). Thus the highest spur level in OSLF technique is 20P log(M) lower than the highest spur in SLF technique.

IV. SIMULATION RESULTS
A 2.4 GHz output PLL with a f r = 20 MHz reference frequency as shown at block level in Fig.7 is simulated to validate the proposed technique. The PLL is a Type-II PLL with two poles at DC, a stabilising zero and two high frequency poles after the unity gain bandwidth to reduce spurs. The parameters of the PLL are chosen to optimise the integrated jitter at the PLL output. The UGB ( f u ) of the Fractional-N PLL is f u ≈ 400 kHz. The zero is placed at f z = 100 kHz, and the poles are at f p1 = 1.67 MHz and f p2 = 8 MHz. The phase margin of the PLL is ≈ 60 0 . The nominal divide value in Integer-N mode is N = 120 and in Fractional-N mode N. f = 120.333. The VCO gain is K v = 200 MHz/V. An offset is introduced in the PFD/CP characteristics by adding a mismatch in the reset path of the UP and DN signals to reduce the Σ − ∆ noise folding into the in-band due to the PFD/CP non-linearity [3], [10], [11], [12]. The MPLL on the other hand was designed to keep its area and power minimum. So the UGB of the MPLL is chosen to the maximum value of f r /10 = 2 MHz. The value of M is chosen to be 4. All the blocks in the PLL are modeled behaviorally except the loop filter (including the CMOS switches) of the Fractional-N PLL and the MPLL, which are at schematic level. The devices used in the sampling switch are from the UMC 180 nm CMOS process. A 5% mismatch in the CP current is modeled as shown in Fig.7. The VCO and the fractional divider were modeled with a combined VCO and divider model to reduce simulation time [13]. A 3 rd -order Σ − ∆ MASH 1-1-1 modulator [14] was used to generate the divide value for the fractional part. To measure the reference spurs, the PLL is simulated in the Fractional-N mode in a transient simulation 3  The phase noise (and the reference spurs) at the PLL output can be estimated by computing the PSD of control voltage and then passing it through the VCO transfer function (|K v /2 f | 2 ) to compute the one-sided PSD as shown in Fig.7.  It can be seen that the added MPLL increases the overall current consumption of the PLL by < 6 % (the power consumed in the Σ − ∆ modulator of the Fractional-N PLL is not included) and the loop filter area by < 2 %. Thus the increase in area and power is not very significant.

V. CONCLUSION
Reference spurs in CP PLLs can be eliminated in both Fractional-N and Integer-N PLLs by applying the proposed OSLF technique. In case of Integer-N PLLs, it was shown that reference spurs can be completely eliminated by an insignificant power and area overhead. In case of Fractional-N PLLs, the reference spurs can be eliminated with an insignificant (< 6 %) increase in power and area.